Abstract: A method is presented for back-end-of-the-line (BEOL) metallization with lines formed by subtractive patterning and vias formed by damascene processes. The method includes depositing a dielectric layer over a conductive layer formed over a substrate, forming spacers surrounding mandrel sections formed over the dielectric layer, selectively depositing gap fill material adjacent the spacers, selectively removing the spacers, etching the dielectric layer and the conductive layer to expose a top surface of the substrate, depositing and planarizing an interlayer dielectric, selectively forming openings in the dielectric layer, and filling the openings with a conductive material to define metal vias.

Abstract: A semiconductor structure includes a substrate, a bottom source/drain region disposed on a top surface of the substrate, and a plurality of fins disposed over a top surface of the bottom source/drain region. The fins provide vertical transport channels for one or more vertical transport field-effect transistors. The semiconductor structure also includes at least one self-aligned shared contact disposed between an adjacent pair of the plurality of fins. The adjacent pair of the plurality of fins includes a first fin providing a first vertical transport channel for a first vertical transport field-effect transistor and a second fin providing a second vertical transport channel for a second vertical transport field-effect transistor.

Abstract: A method of forming a semiconductor structure includes forming a plurality of fins over a top surface of a bottom source/drain region disposed over a top surface of a substrate, the fins providing vertical transport channels for a plurality of vertical transport field-effect transistors. The method also includes forming a first gate conductor surrounding a first one of an adjacent pair of the plurality of fins providing a first vertical transport channel for a first vertical transport field-effect transistor, forming a second gate conductor surrounding a second one of the adjacent pair of the plurality of fins providing a second vertical transport channel for a second vertical transport field-effect transistor, and forming at least one shared gate contact to the first gate conductor and the second gate conductor, the at least one shared gate contact being formed at first ends of the adjacent pair of the plurality of fins.

Abstract: Interconnect structures having subtractive line with damascene second line type are provided. In one aspect, an interconnect structure includes: first metal lines of a first line type disposed on a substrate; and at least one second metal line of a second line type disposed on the substrate between two of the first metal lines, wherein the first line type includes subtractive lines and the second line type includes damascene lines such that the first metal lines have a different metallization structure from the at least one second metal line. A method of forming an interconnect structure is also provided.

Abstract: A method of forming a vertical transport field effect transistor is provided. The method includes forming a vertical fin on a substrate, and a top source/drain on the vertical fin. The method further includes thinning the vertical fin to form a thinned portion, a tapered upper portion, and a tapered lower portion from the vertical fin. The method further includes depositing a gate dielectric layer on the thinned portion, tapered upper portion, and tapered lower portion of the vertical fin, wherein the gate dielectric layer has an angled portion on each of the tapered upper portion and tapered lower portion. The method further includes depositing a work function metal layer on the gate dielectric layer.

Abstract: A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.

Abstract: Disclosed is an illumination device for use with spoked wheels, such as bicycle wheels, wherein the wheel includes a hub portion, a plurality of spokes, and a rim portion. The illumination device includes a power pack, at least one adaptor body, and at least one attachment portion. The power pack having at least one wire, a flexible button cap, a body housing, and circuit board with a switch. The at least one wire including a plurality of light sources. The at least one attachment portion including a clip portion providing for the installation of the at least one adaptor body to the bicycle spokes. The illumination device also includes a holder for the installation of the power pack to the bicycle wheel. Further, the illumination device may include a tubular body located in the internal cavity of the at least one adaptor body.

Abstract: A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.

Abstract: A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.

Abstract: Embodiments of the present invention are directed to a method for increasing the available width of a shallow trench isolation region. In a non-limiting embodiment of the invention, a semiconductor fin is formed over a substrate. A source or drain is formed on a surface of the substrate between the semiconductor fin and the substrate. A liner is formed over a surface of the semiconductor fin and a surface of the substrate is recessed to expose a sidewall of the source or drain. A mask is formed over the semiconductor fin and the liner. The mask is patterned to expose a top surface and a sidewall of the liner. A sidewall of the source or drain is recessed and a shallow trench isolation region is formed on the recessed top surface of the substrate. The shallow trench isolation region is adjacent to the recessed sidewall of the source or drain.

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer. A first interconnect is formed in the first dielectric layer and includes a first top surface, a first bottom surface, and a first sidewall extending from an edge of the first top surface to an edge of the first bottom surface. A second interconnect is formed in the first dielectric layer and includes a second top surface, a second bottom surface, and a second sidewall extending from an edge of the second top surface to an edge of the second bottom surface. A spacing from the edge of the first top surface to the edge of the second top surface is greater than a spacing from the edge of the first bottom surface to the edge of the second bottom surface.

Abstract: Embodiments of the invention include a method of forming a multi-layer integrated circuit (IC) structure that includes forming a first dielectric layer. A first interconnect is formed in the first dielectric layer and includes a first top surface, a first bottom surface, and a first sidewall extending from an edge of the first top surface to an edge of the first bottom surface. A second interconnect is formed in the first dielectric layer and includes a second top surface, a second bottom surface, and a second sidewall extending from an edge of the second top surface to an edge of the second bottom surface. A spacing from the edge of the first top surface to the edge of the second top surface is greater than a spacing from the edge of the first bottom surface to the edge of the second bottom surface.

Abstract: A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.

Abstract: A method of forming an interconnect structure includes forming at least one second-level interconnect in a sacrificial dielectric layer that is formed on an upper surface of a sacrificial etch stop layer, and removing the sacrificial dielectric layer and the sacrificial etch stop layer while maintaining the at least one second-level interconnect so as to expose an underlying dielectric layer. The method further includes depositing a replacement dielectric layer on an upper surface of the underlying dielectric layer to embed the at least one second-level interconnect in the replacement dielectric layer. Accordingly, an interconnect structure can be formed that includes one or more first-level interconnect in a dielectric layer and one or more second-level interconnects in a replacement dielectric layer stacked on the dielectric layer. The replacement dielectric layer directly contacts the dielectric layer.

Abstract: Methods for doping a semiconductor layer include forming a first mask on a first region of a semiconductor layer. A second region of the semiconductor layer, that is not covered by the first mask, is doped. A second mask is formed on the second region of the semiconductor layer. The first mask is etched away. The first region of the semiconductor layer is doped.

Abstract: Embodiments of the present invention are directed to fabrication methods and resulting interconnect structures having a conductive thin metal layer on a top via that promotes the selective growth of the next level interconnect lines (the line above). In a non-limiting embodiment of the invention, a first conductive line is formed in a dielectric layer. A via is formed on the first conductive line and a seed layer is formed on the via and the dielectric layer. A surface of the seed layer is exposed and a second conductive line is deposited onto the exposed surface of the seed layer. In a non-limiting embodiment of the invention, the second conductive line is selectively grown from the seed layer.

Abstract: A technique relates to an integrated circuit (IC). The IC includes a conductive line formed on a conductive via, the conductive line being formed though a dielectric material. The IC includes an etch stop layer having one or more extended portions intervening between one or more edge portions of the conductive line and the conductive via, the one or more edge portions being at a periphery of the conductive line and the conductive via, the etch stop layer including a higher dielectric breakdown than the dielectric material. The one or more extended portions of the etch stop layer cause the conductive line to be formed with a bottom part having a reduced dimension than an upper part of the conductive line.

Abstract: A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element.

Abstract: A method of forming a top via is provided. The method includes forming a sacrificial trench layer and conductive trench plug in an interlayer dielectric (ILD) layer on a conductive line. The method further includes forming a cover layer on the ILD layer, sacrificial trench layer, and conductive trench plug, and forming a sacrificial channel layer and a conductive channel plug on the conductive trench plug. The method further includes removing the cover layer and the ILD layer to expose the sacrificial trench layer and the sacrificial channel layer. The method further includes removing the sacrificial trench layer and the sacrificial channel layer, and forming a barrier layer on the conductive channel plug and conductive trench plug.