Abstract: A top via interconnect with enlarged via top and a fabrication method therefor. One embodiment may comprise a semiconductor interconnect structure, comprising a first dielectric layer having a top surface, a bottom metal line formed in the dielectric layer, a second dielectric layer deposited above the top surface of the first dielectric layer, a via etched through the second dielectric layer above the bottom metal line, wherein the via exposes at least a portion of the top surface of the first dielectric layer, and a metal stud in the via that extends over the exposed at least a portion of the first dielectric layer. The metal stud in the via may further comprise a shoulder surface and a convex top surface.

Abstract: A method of forming a vertical transport field effect transistor (VTFET) is provided. The method includes forming one or more vertical fins on a substrate, wherein there is a fin transition region between each of the one or more vertical fins and the substrate. The method further includes forming a sidewall liner having a first thickness on each of the one or more vertical fins. The method further includes forming a sidewall spacer having a second thickness on each of the sidewall liner(s), wherein the first thickness of the sidewall liner and the second thickness of the sidewall spacer determines an offset distance from each of the one or more vertical fins. The method further includes forming a trench with an edge offset from each of the one or more vertical fins by the offset distance.

Abstract: A sound and illumination device including a sound-making portion, an illumination portion, and an attachment portion for mounting on a bicycle. The sound-making portion including a lever, a spring, a striking portion, and a metal portion, wherein the metal portion covers the lever, the spring, and the striking portion. The lever may include a magnet. The illumination portion including a cover portion, an electrical circuit, a switch, a light emitting source and a power source. Actuation of the lever of the sound-making portion results in the activation of the light emitting source of the illumination portion resulting in the concurrent emission of light and sound.

Abstract: Currently disclosed is a device for increasing visibility of a guy line at night. The device includes a housing, a light emitting source, a power source, and an on/off switch. The housing having an internal portion, external portion, and an attachment mechanism located on the external portion of the housing locking in place the housing to the guy line. The light emitting source is located within the housing and powered by the power source. The on/off switch is in contact with the power source providing readily activation of the light emitting source. The attachment mechanism may comprise at least one hook portion and a tensioning mechanism. The tensioning mechanism may comprise at least one offset portion. The tensioning mechanism prevents the device from sliding down the guy line.

Abstract: A method of manufacturing a semiconductor device is provided. The method includes forming a first trench partially through a first substrate from a first side of the first substrate. The method also includes widening a bottom portion of the first trench to form a lateral footing area of the first trench. The method includes forming a first metallization in the first trench; forming a second trench through a second substrate from a second side of the second substrate to expose at least a portion of first metallization in an area corresponding to the lateral footing area of the first trench, the second side being opposite to the first side. The method also includes forming a second metallization in the second trench in contact with the first metallization.

Abstract: Disclosed is an illumination device for use with spoked wheels, such as bicycle wheels, wherein the wheel includes a hub portion, a plurality of spokes, and a rim portion. The illumination device includes a power pack, at least one adaptor body, and at least one attachment portion. The power pack having at least one wire, a flexible button cap, a body housing, and circuit board with a switch. The at least one wire including a plurality of light sources. The at least one attachment portion including a clip portion providing for the installation of the at least one adaptor body to the bicycle spokes. The illumination device also includes a holder for the installation of the power pack to the bicycle wheel. Further, the illumination device may include a tubular body located in the internal cavity of the at least one adaptor body.

Abstract: A semiconductor structure comprises a front-end-of-line region comprising two or more devices, a first back-end-of-line region on a first side of the front-end-of-line region, the first back-end-of-line region comprising a first set of interconnects for at least a first subset of the two or more devices in the front-end-of-line region, and a second back-end-of-line region on a second side of the front-end-of-line region opposite the first side of the front-end-of-line region, the second back-end-of-line region comprising a second set of interconnects for at least a second subset of the two or more devices in the front-end-of-line region. The semiconductor structure also comprises one or more passthrough vias disposed in the front-end-of-line region, each of the one or more passthrough vias connecting at least one of the first set of interconnects of the first back-end-of-line region to at least one of the second set of interconnects of the second back-end-of-line region.

Abstract: A sound and illumination device including a sound-making portion, an illumination portion, and an attachment portion for mounting on a bicycle. The sound-making portion including a lever, a spring, a striking portion, and a metal portion, wherein the metal portion covers the lever, the spring, and the striking portion. The lever may include a magnet. The illumination portion including a cover portion, an electrical circuit, a switch, a light emitting source and a power source. Actuation of the lever of the sound-making portion results in the activation of the light emitting source of the illumination portion resulting in the concurrent emission of light and sound.

Abstract: Currently disclosed is a device for increasing visibility of a guy line at night. The device includes a housing, a light emitting source, a power source, and an on/off switch. The housing having an internal portion, external portion, and an attachment mechanism located on the external portion of the housing locking in place the housing to the guy line. The light emitting source is located within the housing and powered by the power source. The on/off switch is in contact with the power source providing readily activation of the light emitting source. The attachment mechanism may comprise at least one hook portion and a tensioning mechanism. The tensioning mechanism may comprise at least one offset portion. The tensioning mechanism prevents the device from sliding down the guy line.

Abstract: Disclosed is an illumination device for use with spoked wheels, such as bicycle wheels, wherein the wheel includes a hub portion, a plurality of spokes, and a rim portion. The illumination device includes a power pack, at least one adaptor body, and at least one attachment portion. The power pack having at least one wire, a flexible button cap, a body housing, and circuit board with a switch. The at least one wire including a plurality of light sources. The at least one attachment portion including a clip portion providing for the installation of the at least one adaptor body to the bicycle spokes. The illumination device also includes a holder for the installation of the power pack to the bicycle wheel. Further, the illumination device may include a tubular body located in the internal cavity of the at least one adaptor body.

Abstract: A method comprising forming at least one fin on a substrate, wherein the at least one fin has a first section and a second section. Forming a separating layer on the substrate to isolate the second section of the fin from the first section of the fin. Forming as first set of electrical components on the first section of the at least one fin. Flipping the substrate over and removing the substrate to expose a surface of the second section of the at least one fin. Removing a portion of the second section of the at least one fin, whereby removing a portion of the second section a trench is created between sections of the separating layer and an exposed portion of the at least one fin and forming a hard mask in the trench.

Abstract: A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.

Abstract: A method is presented for back-end-of-the-line (BEOL) metallization with lines formed by subtractive patterning and vias formed by damascene processes. The method includes depositing a dielectric layer over a conductive layer formed over a substrate, forming spacers surrounding mandrel sections formed over the dielectric layer, selectively depositing gap fill material adjacent the spacers, selectively removing the spacers, etching the dielectric layer and the conductive layer to expose a top surface of the substrate, depositing and planarizing an inter-layer dielectric, selectively forming openings in the dielectric layer, and filling the openings with a conductive material to define metal vias.

Abstract: Integrated chips include a dielectric layer that includes at least one trench and at least one plug region. A line is formed in the dielectric layer in the at least one trench and terminates at the plug region. A dielectric plug is formed in the plug region.

Abstract: A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element.

Abstract: Interconnect structures having subtractive line with damascene second line type are provided. In one aspect, an interconnect structure includes: first metal lines of a first line type disposed on a substrate; and at least one second metal line of a second line type disposed on the substrate between two of the first metal lines, wherein the first line type includes subtractive lines and the second line type includes damascene lines such that the first metal lines have a different metallization structure from the at least one second metal line. A method of forming an interconnect structure is also provided.

Abstract: A method of fabricating an integrated circuit includes forming a first trench such that a portion of the first trench is defined by a portion of a first-type of interconnect and depositing a sacrificial spacer liner in the first trench to cover the portion of the first-type of interconnect element. The method further includes forming a dielectric cap on the sacrificial spacer liner and above the first-type of interconnect element, removing the dielectric cap to expose at least a portion of the first-type of interconnect element, and forming a second-type of interconnect element on the exposed first-type of interconnect element.

Abstract: Integrated chips and methods of forming the same include forming conductive lines on an underlying layer, between regions of dielectric material. The regions of dielectric material are selectively patterned, leaving at least one dielectric remnant region. An interlayer dielectric is formed over the underlying layer and the at least one dielectric remnant region, between the conductive lines.

Abstract: A method is presented for constructing fully-aligned top-via interconnects by employing a subtractive etch process. The method includes building a first metallization stack over a substrate, depositing a first lithography stack over the first metallization stack, etching the first lithography stack and the first metallization stack to form a receded first metallization stack, and depositing a first dielectric adjacent the receded first metallization stack. The method further includes building a second metallization stack over the first dielectric and the receded first metallization stack, depositing a second lithography stack over the second metallization stack, etching the second lithography stack and the second metallization stack to form a receded second metallization stack, and trimming the receded first metallization stack to form a via connecting the receded first metallization stack to the receded second metallization stack.

Abstract: A method for fabricating a semiconductor device including a self-aligned top via includes subtractively etching a conductive layer to form at least a first conductive line on a substrate. After the subtractive etching, the method further includes forming a barrier layer along the substate and along the first conductive line, planarizing at least portions of the barrier layer to obtain at least an exposed first conductive line, recessing at least the exposed first conductive line to form a first recessed conductive line, and forming conductive material in a via opening on the first recessed conductive line.