Abstract: This document discloses techniques, apparatuses, and systems for connecting semiconductor dies through traces. A semiconductor assembly is described that includes two semiconductor dies. The first semiconductor die includes a first dielectric layer at which first circuitry is disposed. The second semiconductor die includes a second dielectric layer at which second circuitry is disposed. One or more traces extend from a side surface of the first dielectric layer and at a side surface of the second dielectric layer to electrically couple the first circuitry and the second circuitry. In doing so, rigid connective structures may not be needed to couple the first semiconductor die and the second semiconductor die.

Abstract: Semiconductor devices and semiconductor device assemblies, and related systems and methods, are disclosed herein. In some embodiments, the semiconductor device includes a support substrate, a first die package carried by the support substrate, and a second die package carried by the first die package. Each of the first and second die packages can include a first die, a second die hybrid bonded a surface of the first die, and a third die hybrid bonded to a surface of the second die. The first die is coupled to the third die via an interconnect portion of the second die. Further, the third die can include an array of active cells for each of the packages, the second die can include complementary-metal-oxide-semiconductor (CMOS) circuitry accessing the active cells, and the first die can include backend of line (BEOL) circuitry associated with the active cells and CMOS circuitry.

Abstract: Methods of making a semiconductor device assembly are provided. The methods can comprise providing a first semiconductor device having a first dielectric material at a first surface, providing a carrier wafer having a second dielectric material at a second surface, and forming a dielectric-dielectric bond between the first dielectric material and the second dielectric material. At least one of the first surface and the second surface includes a cavity configured to entrap a gas during the formation of the bond. The method can further include stacking one or more second semiconductor devices over the first semiconductor device to form the semiconductor device assembly, and removing the semiconductor device assembly from the carrier wafer.

Abstract: A semiconductor device assembly comprises a package substrate including (i) an upper surface having a plurality of internal contacts, (ii) a lower surface having a plurality of external contacts coupled to the plurality of internal contacts, and (iii) a cavity extending into the package substrate. The assembly further comprises a stack of first semiconductor devices disposed in the cavity, an uppermost first semiconductor device of the stack having a plurality of stack contacts, and an interposer including (i) a bottom surface having a first plurality of lower contacts coupled to the plurality of stack contacts and a second plurality of lower contacts coupled to the plurality of internal contacts, and (ii) a top surface having a plurality of upper contacts coupled to the first and second pluralities of lower contacts. The assembly further comprises a second semiconductor device including a plurality of die contacts coupled to the plurality of upper contacts.

Abstract: This document discloses techniques, apparatuses, and systems for providing a semiconductor device assembly with a substrate for vertically assembled semiconductor dies. A semiconductor assembly is described that includes a semiconductor die coupled to a substrate such that an active surface of the semiconductor die is substantially orthogonal to a top surface of the substrate. The substrate includes a surface having a recessed slot at which a side surface of the semiconductor die couples. The semiconductor die includes a contact pad that couples to a contact pad at the recessed slot. In doing so, the techniques, apparatuses, and systems herein enable a robust and cost-efficient semiconductor device to be assembled.

Abstract: Stacked semiconductor assemblies, and related systems and methods, are disclosed herein. A representative stacked semiconductor assembly can include a lowermost die and two or more modules carried by an upper surface of the lowermost die. Each of the module(s) can include a base die and one or more upper dies and/or an uppermost die carried by the base die. Each of the dies in the module is coupled via hybrid bonds between adjacent dies. Further, the base die in a lowermost module is coupled to the lowermost die by hybrid bonds. As a result of the modular construction, the lowermost die can have a first longitudinal footprint, the base die in each of the module(s) can have a second longitudinal footprint smaller than the first longitudinal footprint, and each of the upper die(s) and/or the uppermost die can have a third longitudinal footprint smaller than the second longitudinal footprint.

Abstract: A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.

Abstract: A semiconductor device assembly that includes carbon nanofibers (CNFs) for heat dissipation has a CNF layer. Molding compound encapsulates the CNF layer to form an encapsulated CNF layer. The molding compound extends between individual adjacent CNFs within the encapsulated CNF layer, and upper edges of at least a portion of individual CNFs within the encapsulated CNF layer are exposed along an upper surface of the encapsulated CNF layer. The upper surface of the CNF layer is removably attached to a bottom surface of a carrier wafer.

Abstract: Systems and methods for semiconductor devices having a substrate with bond pads, a die pair in a stacked configuration above the bond pads and having a first die having an oxide layer, a second die having an oxide layer attached to the first oxide layer, and conductive bonds electrically coupling the dies. Interconnects extend between the bond pads and the die pair, electrically coupling die pair to the substrate. The device may include a second die pair electrically coupled to: (1) the first die pair with secondary interconnects; and (2) the substrate with through-silicon vias extending through the first die pair. The top die of a die pair may be a thick die for use at the top of a pair stack. Pairs may be created by matching dies of a first silicon wafer to dies of a second silicon wafer, combination bonding the wafers, and dicing the die pairs.

Abstract: A semiconductor device includes a substrate; a die attached over the substrate; and a metal enclosure continuously encircling a space and extending vertically between the substrate and the die.

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material sintering therein.

Abstract: A semiconductor device having monolithic conductive columns, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, a non-conductive liner, and a plug of non-conductive material. The conductive pad may be at a surface of the semiconductor substrate. The opening may extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the plug may fill the opening. A second opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

Abstract: A semiconductor device having monolithic conductive cylinders, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, and a top dielectric layer. The conductive pad may be at a first surface of the semiconductor substrate. The opening may be ring-shaped and extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the top dielectric layer may cover the second surface and may fill the opening. A second ring-shaped opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

Abstract: A semiconductor device having monolithic conductive cylinders, and associated systems and methods, are disclosed herein. The semiconductor device can include a semiconductor substrate, a conductive pad, an opening, and a top dielectric layer. The conductive pad may be at a first surface of the semiconductor substrate. The opening may be ring-shaped and extend through the semiconductor substrate from the conductive pad to a second surface and define a side wall. The liner may coat the side wall and the top dielectric layer may cover the second surface and may fill the opening. A second ring-shaped opening may be formed through the semiconductor device and the opening and a conductive material plated therein.

Abstract: A semiconductor package can include a semiconductor die stack including a top die and one or more core dies below the top die. The semiconductor package can further include a metal heat sink plated on a top surface of the top die and have a plurality of side surfaces coplanar with corresponding ones of a plurality of sidewalls of the semiconductor die stack. A molding can surround the stack of semiconductor dies and the metal heat sink, the molding including a top surface coplanar with an exposed upper surface of the metal heat sink. The top surface of the molding and the exposed upper surface of the metal heat sink are both mechanically altered. For example, the metal heat sink and the molding can be simultaneously ground with a grinding disc and can show grinding marks as a result.

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.

Abstract: A semiconductor device assembly including a shape-memory element connected to at least one component of the semiconductor device assembly. The shape-memory element may be temperature activated or electrically activated. The shape-memory element is configured to move to reduce, minimize, or modify a warpage of a component of the assembly by moving to an initial shape. The shape-memory element may be applied to a surface of a component of the semiconductor device assembly or may be positioned within a component of the semiconductor device assembly such as a layer. The shape-memory element may be connected between two components of the semiconductor device assembly. A plurality of shape-memory elements may be used to reduce, minimize, and/or modify warpage of one or more components of a semiconductor device assembly.

Abstract: Bond pads for semiconductor die assemblies, and associated methods and systems are disclosed. In one embodiment, a semiconductor die assembly includes a first semiconductor die including a first bond pad on a first side of the first semiconductor die. The semiconductor die assembly further includes a second semiconductor die including a second bond pad on a second side of the second semiconductor die. The first bond pad is aligned and bonded to the second bond pad at a bonding interface between the first and second bond pads, and at least one of the first and second bond pads include a first metal and a second metal different than the first metal. Further, the first metal is located at the bonding interface and the second metal has a first thickness corresponding to at least one-fourth of a second thickness of the first or second bond pad.

Abstract: Disclosed is a microelectronic device assembly comprising a substrate having conductors exposed on a surface thereof. Two or more microelectronic devices are stacked on the substrate, each microelectronic device comprising an active surface having bond pads operably coupled to conductive traces extending over a dielectric material to via locations beyond at least one side of the stack, and vias extending through the dielectric materials at the via locations and comprising conductive material in contact with at least some of the conductive traces of each of the two or more electronic devices and extending to exposed conductors of the substrate. Methods of fabrication and related electronic systems are also disclosed.

Abstract: A thermocompression bonding (TCB) apparatus can include a wall having a height measured in a first direction and configured to be positioned between a first pressing surface and a second pressing surface of a semiconductor bonding apparatus. The apparatus can include a cavity at least partially surrounded by the wall, the cavity sized to receive a semiconductor substrate and a stack of semiconductor dies positioned between the semiconductor substrate and the first pressing surface, the stack of semiconductor dies and semiconductor substrate having a combined unpressed stack height as measured in the first direction. In some embodiments, the unpressed stack height is greater than the height of the wall, and the wall is configured to be contacted by the first pressing surface to limit movement of the first pressing surface toward the second pressing surface during a semiconductor bonding process.