Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method for manufacturing a plurality of microelectronic imaging units includes placing a plurality of singulated imaging dies on a support member. The individual imaging dies include a first height, an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes electrically connecting the external contacts of the imaging dies to corresponding terminals on the support member and forming a base on the support member between adjacent imaging dies. The base has a second height less than or approximately equal to the first height of the dies. The method further includes attaching a plurality of covers to the base so that the covers are positioned over corresponding image sensors.

Abstract: Methods for manufacturing microelectronic imaging units and microelectronic imaging units that are formed using such methods are disclosed herein. In one embodiment, a method includes providing a plurality of imaging dies on a microfeature workpiece. The individual imaging dies include an image sensor, an integrated circuit operably coupled to the image sensor, and a plurality of external contacts operably coupled to the integrated circuit. The method further includes attaching a plurality of covers to corresponding imaging dies, cutting the microfeature workpiece to singulate the imaging dies, and coupling the singulated dies to a support member. The covers can be attached to the imaging dies before or after the workpiece is cut.

Abstract: A stereolithographically fabricated heat sink may include non-linear, or convoluted passageways therethrough, through which air can flow. The heat sink may also include a heat dissipation element that is configured to release heat as air flows past a surface thereof. As at least a portion of the heat sink is stereolithographically fabricated, that portion can have a series of superimposed, contiguous, mutually adhered layers of thermally conductive material.

Abstract: A method used for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multilevel laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.

Abstract: Programmed material consolidation processes for fabricating heat sinks include the selective consolidation of previously unconsolidated material. The heat dissipation element of the heat sink that has been fabricated by such processes can have non-linear or convoluted passageways therethrough to enhance air flow. An optical recognition system may be used in conjunction with programmed material consolidation processes to ensure that a heat sink is fabricated or positioned on the appropriate location of an electronic component, such as a semiconductor device.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: The present invention provides a method and apparatus for marking a semiconductor wafer or device. The method and apparatus have particular application to wafers or devices which have been subjected to a thinning process, including backgrinding in particular. The present method comprises reducing the cross-section of a wafer or device, applying a tape having optical energy-markable properties over a surface or edge of the wafer or device, and exposing the tape to an optical energy source to create an identifiable mark. A method for manufacturing an integrated circuit chip and for identifying a known good die are also disclosed. The apparatus of the present invention comprises a multilevel laser-markable tape for application to a bare semiconductor die. In the apparatus, an adhesive layer of the tape provides a homogenous surface for marking subsequent to exposure to electromagnetic radiation.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: A stereolithographically fabricated heat sink includes a heat transfer element cofigured to be disposed proximate a semiconductor device so as to absorb heat from the semiconductor device during use thereof. The heat sink also has a heat dissipation element that is configured to release heat as air flows past a surface thereof. When stereolithographic processes are used to fabricate the heat dissipation element of the heat sink, the heat dissipation element can have non-linear, or convoluted passageways formed therethrough, through which air can flow. As at least a portion of the heat sink is stereolithographically fabricated, that portion can have a series of superimposed, contiguous, mutually adhered layers of thermally conductive material. The layers can be fabricated by consolidated selected regions of a layer of unconsolidated particulate or powdered material, or by defining an object layer from a sheet of material.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die-attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection bumps on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of “known good dice” (KGD) rework procedures during repair is eliminated.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.

Abstract: A method and apparatus for encapsulating a BGA package. Specifically, a BGA package is encapsulated after the balls are attached to the package. The backside of the package having the balls disposed thereon may be completely covered by the encapsulant. The encapsulant is disposed in direct contact about a portion of the balls. A liner is provided to facilitate the formation of an unencapsulated portion of each ball. The unencapsulated portion may be used to couple the package to a system.

Abstract: Flip-chip semiconductor assemblies, each including integrated circuit (IC) dice and an associated substrate, are electrically tested before encapsulation using an in-line or in-situ test socket or probes at a die-attach station. Those assemblies using “wet” quick-cure epoxies for die attachment may be tested prior to the epoxy being cured by pressing the integrated circuit (IC) dice against interconnection points on the substrate for electrical connection, while those assemblies using “dry” epoxies may be cured prior to testing. In either case, any failures in the dice or in the interconnections between the dice and the substrates can be easily fixed, and the need for the use of known-good-die (KGD) rework procedures during repair is eliminated.