Patents by Inventor Brian C. Gaide

Brian C. Gaide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 12271332
    Abstract: A 3D stacked device includes a plurality of semiconductor chips stacked in a vertical direction. The semiconductor chips each include a plurality of portions grouped into slivers according to the column they lie in. Each of the portions further includes a plurality of blocks grouped into sub-slivers and interconnected by inter-block bridges. A block that must be functional on the bottommost chip of the 3D stacked device is configured to bypass a neighboring nonfunctional block on the same chip by using a communication path of an inter-block bridge to a neighboring functional block that is in the same sub-sliver as the nonfunctional block but in a different chip. So long as only one of the blocks in a sub-sliver is nonfunctional, the inter-block bridges permit the other blocks in the sub-sliver to receive and route data.
    Type: Grant
    Filed: March 30, 2023
    Date of Patent: April 8, 2025
    Assignee: XILINX, INC.
    Inventor: Brian C. Gaide
  • Patent number: 12261603
    Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.
    Type: Grant
    Filed: May 18, 2023
    Date of Patent: March 25, 2025
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
  • Patent number: 12235671
    Abstract: An integrated circuit (IC) device includes a circuit comprising pipeline stages, and a controller circuitry configured to: load a static value into each of the pipeline stages based on a change in a clock enable (CE) signal, and sequentially deactivate each of the pipeline stages after a quantity of cycles of a reference clock signal that occur after the change of the CE signal, wherein the quantity of the cycles of the clock signal is based on a quantity of the pipeline stages.
    Type: Grant
    Filed: May 19, 2023
    Date of Patent: February 25, 2025
    Assignee: XILINX, INC.
    Inventor: Brian C. Gaide
  • Patent number: 12154617
    Abstract: A yield recovery scheme for configuration memory of an IC device includes asserting an override configuration value on a bitline of memory cells of the configuration memory, where a data node of a faulty one of the memory cells is coupled to a node of configurable circuitry of the IC device, and asserting a wordline of the faulty memory cell while the override configuration value is asserted on the bitline to couple the bitline to the node of the configurable circuitry through the faulty memory cell (i.e., to force a state of the data node to the override configuration value). An identifier of the faulty memory cell may be stored on the IC device (e.g., E-fuses), and control circuitry of the IC device may retrieve the identifier to configure override circuitry of the IC device.
    Type: Grant
    Filed: September 21, 2022
    Date of Patent: November 26, 2024
    Assignee: XILINX, INC.
    Inventor: Brian C. Gaide
  • Patent number: 12093394
    Abstract: Some examples described herein provide for securely booting a heterogeneous integration circuitry apparatus. In an example, an apparatus (e.g., heterogeneous integration circuitry) includes a first portion and a second portion of one or more entropy sources on a first component and a second component, respectively. The apparatus also includes a key generation circuit communicatively coupled with the first portion and the second portion to generate a key encrypted key based on a first set of bits output by the first portion and a second set of bits output by the second portion. The apparatus also includes a key security circuit to generate, based on the key encrypted key and an encrypted public key stored at the apparatus, a plaintext public key to be used by a boot loader during a secure booting operation for the apparatus.
    Type: Grant
    Filed: February 20, 2023
    Date of Patent: September 17, 2024
    Assignee: XILINX, INC.
    Inventors: Aman Gupta, James D. Wesselkamper, James Anderson, Nader Sharifi, Ahmad R. Ansari, Sagheer Ahmad, Brian C. Gaide
  • Patent number: 11901300
    Abstract: A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having third slots is formed on the first side between the first and second regions, each slot having an identical third bond pad layout. A pad density of the third bond pad layout is greater than the first bond pad layout. One of the third slots is coupled to contact pads disposed in a region not directly below any of the second slots.
    Type: Grant
    Filed: February 22, 2022
    Date of Patent: February 13, 2024
    Assignee: XILINX, INC.
    Inventors: Jaspreet Singh Gandhi, Brian C. Gaide
  • Patent number: 11868174
    Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.
    Type: Grant
    Filed: December 18, 2020
    Date of Patent: January 9, 2024
    Assignee: XILINX, INC.
    Inventor: Brian C. Gaide
  • Publication number: 20230291405
    Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.
    Type: Application
    Filed: May 18, 2023
    Publication date: September 14, 2023
    Applicant: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
  • Patent number: 11750195
    Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.
    Type: Grant
    Filed: July 28, 2022
    Date of Patent: September 5, 2023
    Assignee: XILINX, INC.
    Inventors: Steven P. Young, Brian C. Gaide
  • Patent number: 11683038
    Abstract: A System-on-Chip includes a first partition configured to implement a first application using of at least a first portion of one or more of a plurality of subsystems of the System-on-Chip and a second partition configured to implement a second application concurrently with the first partition. The second application uses at least a second portion of one or more of the plurality of subsystems. The first partition is isolated from the second partition.
    Type: Grant
    Filed: June 17, 2021
    Date of Patent: June 20, 2023
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
  • Patent number: 11451230
    Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.
    Type: Grant
    Filed: April 23, 2020
    Date of Patent: September 20, 2022
    Assignee: XILINX, INC.
    Inventors: Steven P. Young, Brian C. Gaide
  • Patent number: 11270977
    Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: March 8, 2022
    Assignee: XILINX, INC.
    Inventors: Praful Jain, Steven P. Young, Martin L. Voogel, Brian C. Gaide
  • Patent number: 11239203
    Abstract: Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective neighboring pair directly bonded to a backside of the other chip of the respective neighboring pair. Each of the interchangeable chips has a same processing integrated circuit and a same hardware layout. The chip stack can include a distal chip, which can be directly bonded to a second one of the plurality of interchangeable chips.
    Type: Grant
    Filed: November 1, 2019
    Date of Patent: February 1, 2022
    Assignee: XILINX, INC.
    Inventors: Brian C. Gaide, Steven P. Young
  • Patent number: 11063594
    Abstract: An integrated circuit (IC) includes a first interface configured for operation with a plurality of tenants implemented concurrently in the integrated circuit, wherein the plurality of tenants communicate with a host data processing system using the first interface. The IC includes a second interface configured for operation with the plurality of tenants, wherein the plurality of tenants communicate with one or more network nodes via a network using the second interface. The IC can include a programmable logic circuitry configured for operation with the plurality of tenants, wherein the programmable logic circuitry implements one or more hardware accelerated functions for the plurality of tenants and routes data between the first interface and the second interface. The first interface, the second interface, and the programmable logic circuitry are configured to provide isolation among the plurality of tenants.
    Type: Grant
    Filed: May 11, 2020
    Date of Patent: July 13, 2021
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
  • Patent number: 10998904
    Abstract: Configurable termination circuits for use with programmable logic devices are disclosed. In one implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to a fixed voltage. In another implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to an output of the one or more configurable logic blocks. In some implementations, the programmable logic device may include a platform management controller to configure the termination circuits based on configuration data.
    Type: Grant
    Filed: November 15, 2019
    Date of Patent: May 4, 2021
    Assignee: Xilinx, Inc.
    Inventors: Sundeep Ram Gopal Agarwal, Brian C. Gaide, Ramakrishna Kishore Tanikella
  • Patent number: 10871796
    Abstract: In some examples, a system includes a clock source, a clock distribution network, and a plurality of clock generators. The clock source is configured to generate a global clocking signal. The clock distribution network is configured to fan out the global clocking signal to a plurality of loads. The plurality of clock generators is configured to receive the global clocking signal through the clock distribution network. Each clock generator of the plurality of clock generators is configured to generate a related clocking signal to the global clocking signal from the received global clocking signal. Each clock generator of the plurality of clock generators maybe configured to supply the global clocking signal or the related clocking signal to its respective load of the plurality of loads.
    Type: Grant
    Filed: August 6, 2019
    Date of Patent: December 22, 2020
    Assignee: XILINX, INC.
    Inventors: Brian C. Gaide, Chiao K. Hwang, Guoqing Ning, Richard W. Swanson, Wayne E. Wennekamp
  • Patent number: 10825772
    Abstract: Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.
    Type: Grant
    Filed: September 16, 2019
    Date of Patent: November 3, 2020
    Inventors: Steven P. Young, Brian C. Gaide
  • Patent number: 10741524
    Abstract: Examples herein describe techniques for forming 3D stacked devices which include a redundant logical layer. The 3D stacked devices include a plurality of semiconductor chips stacked in a vertical direction such that each chip is bonded to a chip above, below, or both in the stack. In one embodiment, each chip is the same—e.g., has the same circuitry arranged in the same configuration in the chip. The 3D stacked device provides a redundant logic layer by dividing the chips into a plurality of slivers which are interconnected by inter-chip bridges. For example, the 3D stacked device may include three stacked chips that are divided into three different slivers where each sliver includes a portion from each of the chips. So long as only one of portions in a sliver is nonfunctional, the inter-chip bridges permit the other portions in the sliver to receive and route data.
    Type: Grant
    Filed: April 30, 2018
    Date of Patent: August 11, 2020
    Assignee: XILINX, INC.
    Inventors: Brian C. Gaide, Matthew H. Klein
  • Patent number: 10715149
    Abstract: A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.
    Type: Grant
    Filed: July 16, 2019
    Date of Patent: July 14, 2020
    Assignee: XILINX, INC.
    Inventors: Eric F. Dellinger, Jay T. Young, Brian C. Gaide, Chirag Ravishankar, Davis Moore, Steven P. Young
  • Patent number: 10673439
    Abstract: A device can include programmable logic circuitry, a processor system coupled to the programmable logic circuitry, and a network-on-chip. The network-on-chip is coupled to the programmable logic circuitry and the processor system. The network-on-chip is programmable to establish user specified data paths communicatively linking a circuit block implemented in the programmable logic circuitry and the processor system. The programmable logic circuitry, the network-on-chip, and the processor system are configured using a platform management controller.
    Type: Grant
    Filed: March 27, 2019
    Date of Patent: June 2, 2020
    Assignee: Xilinx, Inc.
    Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick