Patents by Inventor Brian C. Gaide
Brian C. Gaide has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240103562Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.Type: ApplicationFiled: November 28, 2023Publication date: March 28, 2024Inventor: Brian C. GAIDE
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Publication number: 20240096405Abstract: A yield recovery scheme for configuration memory of an IC device includes asserting an override configuration value on a bitline of memory cells of the configuration memory, where a data node of a faulty one of the memory cells is coupled to a node of configurable circuitry of the IC device, and asserting a wordline of the faulty memory cell while the override configuration value is asserted on the bitline to couple the bitline to the node of the configurable circuitry through the faulty memory cell (i.e., to force a state of the data node to the override configuration value). An identifier of the faulty memory cell may be stored on the IC device (e.g., E-fuses), and control circuitry of the IC device may retrieve the identifier to configure override circuitry of the IC device.Type: ApplicationFiled: September 21, 2022Publication date: March 21, 2024Inventor: Brian C. GAIDE
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Patent number: 11901300Abstract: A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having third slots is formed on the first side between the first and second regions, each slot having an identical third bond pad layout. A pad density of the third bond pad layout is greater than the first bond pad layout. One of the third slots is coupled to contact pads disposed in a region not directly below any of the second slots.Type: GrantFiled: February 22, 2022Date of Patent: February 13, 2024Assignee: XILINX, INC.Inventors: Jaspreet Singh Gandhi, Brian C. Gaide
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Patent number: 11868174Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.Type: GrantFiled: December 18, 2020Date of Patent: January 9, 2024Assignee: XILINX, INC.Inventor: Brian C. Gaide
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Publication number: 20230291405Abstract: A System-on-Chip includes a data processing engine array. The data processing engine array includes a plurality of data processing engines organized in a grid. The plurality of data processing engines are partitioned into at least a first partition and a second partition. The first partition includes one or more first data processing engines of the plurality of data processing engines. The second partition includes one or more second data processing engines of the plurality of data processing engines. Each partition is configured to implement an application that executes independently of the other partition.Type: ApplicationFiled: May 18, 2023Publication date: September 14, 2023Applicant: Xilinx, Inc.Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
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Patent number: 11750195Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.Type: GrantFiled: July 28, 2022Date of Patent: September 5, 2023Assignee: XILINX, INC.Inventors: Steven P. Young, Brian C. Gaide
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Publication number: 20230268280Abstract: A universal interposer for an integrated circuit (IC) device has a body having a first surface and a second surface opposite the first surface. A first region is formed on a first side of the body along a first edge. The first region has first slots, each having an identical first bond pad layout. A second region is formed on the first side along a second edge, opposite the first edge. The second region has second slots having an identical second bond pad layout. A third region having third slots is formed on the first side between the first and second regions, each slot having an identical third bond pad layout. A pad density of the third bond pad layout is greater than the first bond pad layout. One of the third slots is coupled to contact pads disposed in a region not directly below any of the second slots.Type: ApplicationFiled: February 22, 2022Publication date: August 24, 2023Inventors: Jaspreet Singh GANDHI, Brian C. GAIDE
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Patent number: 11683038Abstract: A System-on-Chip includes a first partition configured to implement a first application using of at least a first portion of one or more of a plurality of subsystems of the System-on-Chip and a second partition configured to implement a second application concurrently with the first partition. The second application uses at least a second portion of one or more of the plurality of subsystems. The first partition is isolated from the second partition.Type: GrantFiled: June 17, 2021Date of Patent: June 20, 2023Assignee: Xilinx, Inc.Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
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Publication number: 20220368330Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.Type: ApplicationFiled: July 28, 2022Publication date: November 17, 2022Inventors: Steven P. YOUNG, Brian C. GAIDE
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Patent number: 11451230Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.Type: GrantFiled: April 23, 2020Date of Patent: September 20, 2022Assignee: XILINX, INC.Inventors: Steven P. Young, Brian C. Gaide
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Publication number: 20220197329Abstract: Examples described herein generally relate to clock tree routing in a chip stack. In an example, a multi-chip device includes a chip stack. The chip stack includes chips. The chip stack includes a clock tree. In-chip routing of the clock tree is contained within one logical chip of the chip stack. The chip stack includes leaf nodes disposed in respective chips. Each leaf node of the leaf nodes is electrically connected to the clock tree through a respective leaf-level connection bridge. The respective leaf-level connection bridge extends in an out-of-chip direction through a plurality of the chips.Type: ApplicationFiled: December 18, 2020Publication date: June 23, 2022Inventor: Brian C. GAIDE
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Patent number: 11270977Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.Type: GrantFiled: November 8, 2019Date of Patent: March 8, 2022Assignee: XILINX, INC.Inventors: Praful Jain, Steven P. Young, Martin L. Voogel, Brian C. Gaide
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Patent number: 11239203Abstract: Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective neighboring pair directly bonded to a backside of the other chip of the respective neighboring pair. Each of the interchangeable chips has a same processing integrated circuit and a same hardware layout. The chip stack can include a distal chip, which can be directly bonded to a second one of the plurality of interchangeable chips.Type: GrantFiled: November 1, 2019Date of Patent: February 1, 2022Assignee: XILINX, INC.Inventors: Brian C. Gaide, Steven P. Young
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Publication number: 20210336622Abstract: An example integrated circuit includes an array of circuit tiles; interconnect coupling the circuit tiles in the array, the interconnect including interconnect tiles each having a plurality of connections that include at least a connection to a respective one of the circuit tiles and a connection to at least one other interconnect tile; and a plurality of local crossbars in each of the interconnect tiles, the plurality of local crossbars coupled to form a non-blocking crossbar, each of the plurality of local crossbars including handshaking circuitry for asynchronous communication.Type: ApplicationFiled: April 23, 2020Publication date: October 28, 2021Inventors: Steven P. YOUNG, Brian C. GAIDE
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Patent number: 11063594Abstract: An integrated circuit (IC) includes a first interface configured for operation with a plurality of tenants implemented concurrently in the integrated circuit, wherein the plurality of tenants communicate with a host data processing system using the first interface. The IC includes a second interface configured for operation with the plurality of tenants, wherein the plurality of tenants communicate with one or more network nodes via a network using the second interface. The IC can include a programmable logic circuitry configured for operation with the plurality of tenants, wherein the programmable logic circuitry implements one or more hardware accelerated functions for the plurality of tenants and routes data between the first interface and the second interface. The first interface, the second interface, and the programmable logic circuitry are configured to provide isolation among the plurality of tenants.Type: GrantFiled: May 11, 2020Date of Patent: July 13, 2021Assignee: Xilinx, Inc.Inventors: Sagheer Ahmad, Jaideep Dastidar, Brian C. Gaide, Juan J. Noguera Serra, Ian A. Swarbrick
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Publication number: 20210143127Abstract: An apparatus includes a first die including a first substrate with first TSVs running through it, a first top metal layer and first chimney stack vias (CSVs) connecting the first TSVs with the first top metal layer. The apparatus further includes an uppermost die including an uppermost substrate and an uppermost top metal layer, and uppermost CSVs connecting the uppermost substrate with the uppermost top metal layer. The first and uppermost dies are stacked face to face, the first TSVs and the first CSVs are mutually aligned, and the dies are configured such that current is delivered to the apparatus from the first TSVs up through the first CSVs, the first and uppermost top metal layers, and the uppermost CSVs.Type: ApplicationFiled: November 8, 2019Publication date: May 13, 2021Applicant: Xilinx, Inc.Inventors: Praful JAIN, Steven P. YOUNG, Martin L. VOOGEL, Brian C. GAIDE
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Publication number: 20210134760Abstract: Examples described herein generally related to multi-chip devices having vertically stacked chips. In an example, a multi-chip device includes a chip stack. The chip stack includes a base chip and a plurality of interchangeable chips. The base chip is directly bonded to a first one of the plurality of interchangeable chips. Each neighboring pair of the plurality of interchangeable chips is directly bonded together in an orientation with a front side of one chip of the respective neighboring pair directly bonded to a backside of the other chip of the respective neighboring pair. Each of the interchangeable chips has a same processing integrated circuit and a same hardware layout. The chip stack can include a distal chip, which can be directly bonded to a second one of the plurality of interchangeable chips.Type: ApplicationFiled: November 1, 2019Publication date: May 6, 2021Inventors: Brian C. GAIDE, Steven P. YOUNG
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Patent number: 10998904Abstract: Configurable termination circuits for use with programmable logic devices are disclosed. In one implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to a fixed voltage. In another implementation, the termination circuit may include one or more components to couple unused inputs of one or more configurable logic blocks to an output of the one or more configurable logic blocks. In some implementations, the programmable logic device may include a platform management controller to configure the termination circuits based on configuration data.Type: GrantFiled: November 15, 2019Date of Patent: May 4, 2021Assignee: Xilinx, Inc.Inventors: Sundeep Ram Gopal Agarwal, Brian C. Gaide, Ramakrishna Kishore Tanikella
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Patent number: 10871796Abstract: In some examples, a system includes a clock source, a clock distribution network, and a plurality of clock generators. The clock source is configured to generate a global clocking signal. The clock distribution network is configured to fan out the global clocking signal to a plurality of loads. The plurality of clock generators is configured to receive the global clocking signal through the clock distribution network. Each clock generator of the plurality of clock generators is configured to generate a related clocking signal to the global clocking signal from the received global clocking signal. Each clock generator of the plurality of clock generators maybe configured to supply the global clocking signal or the related clocking signal to its respective load of the plurality of loads.Type: GrantFiled: August 6, 2019Date of Patent: December 22, 2020Assignee: XILINX, INC.Inventors: Brian C. Gaide, Chiao K. Hwang, Guoqing Ning, Richard W. Swanson, Wayne E. Wennekamp
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Patent number: 10825772Abstract: Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.Type: GrantFiled: September 16, 2019Date of Patent: November 3, 2020Inventors: Steven P. Young, Brian C. Gaide