Abstract: A register circuit adapted to store data is described. The register circuit comprises a master-slave flip flop coupled to receive the data to be stored by the master-slave flip flop at an input; and a delay element coupled to the master-slave flip flop, the delay element receiving a reference clock signal and generating a slave clock signal the slave clock signal which is delayed relative to a master clock signal. A method of storing data in a register circuit is also described.

Abstract: A circuit for shifting bussed data includes a first column of shift blocks, a compare block, and a second column of multiplexer blocks. The first column shifts the bussed data by a number of bits specified by first bits of a shift control input. The compare block determines the value of a second bit of the shift control input and creates an output reflecting that value. The second column has a control input coupled to the output of the compare block, shifts the data by one byte when the second bit of the shift control input has a first value, and does not shift the data when the second bit has a second value. The shift, compare, and multiplexer blocks can be substantially similar logic blocks programmable to perform any of these functions, can include N-bit data inputs and outputs, and can operate on the bussed data as an N-bit bus.

Abstract: An apparatus includes an integrated circuit with a clock network in an array of circuit blocks. The clock network includes routing tracks, distribution spines, and clock leaves. The routing tracks and the distribution spines are bidirectional.

Abstract: A method and apparatus to test the inter-die interface between two or more semiconductor die in die stacking applications, where a mismatch exists between the number of input and output pads on a base die and the number of input and output pads on a stacked die. In a first embodiment, a number of through-die vias (TDVs) may be used to implement inter-die signal paths using standard or flexible design rules to maintain statistical TDV yield despite the lack of continuity verification of the inter-die signals paths. In alternate embodiments, programmable multiplexers may be utilized to share one or more inter-die connections between the base die and the one or more stacked die so as to facilitate testing and normal operation of each inter-die connection. In other embodiments, spare TDVs are utilized only during test operations, so as to accommodate the mismatch.

Abstract: A circuit for asynchronously transmitting data in an integrated circuit is described. The circuit comprises a transmitter circuit generating data to be transmitted at an output; a first register having an input, an output and a clock input, wherein the input of the first register is coupled to the output of the transmitter and the clock input of the first register is coupled to receive a clock signal; at least one asynchronous buffer having an input and an output, wherein the input is coupled to the output of the first register; a receiver circuit coupled to the output of the at least one buffer; and a second register having an input, and output and a clock input, wherein the input of the at least one asynchronous buffer is coupled to the output of the transmitter and the clock input of the second register is coupled to receive the clock signal. A method of implementing of asynchronously transmitting data in an integrated circuit device is also disclosed.

Abstract: A method of pipelining a data path in an integrated circuit is described. The method comprises receiving a circuit design to be implemented in the integrated circuit device; providing a placement of the circuit design in the integrated circuit device; identifying a most critical path of the placement; adding pipeline registers to the most critical path; and adding pipeline registers to all paths that are parallel to the most critical path. A computer program product for pipelining a data path in an integrated circuit is also described.

Abstract: Integrated circuits having groups of flip-flops with the option to ignore control signals are disclosed. For example, an integrated circuit comprises a first group and a second group of flip-flops that share a common reset signal, and a first selection unit for selecting a first output from among the common reset signal and a logical low signal to be sent to the second group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the second group. The integrated circuit may also include a second selection unit for selecting a second output from among the common reset signal and a logical low signal to be sent to the first group of flop-flops. A selection of the logical low signal is for preventing the common reset signal from being applied to the flip-flops in the first group.

Abstract: In an apparatus, an interconnect block includes a plurality of configuration memory cells. A plurality of multiplexers is respectively coupled to the configuration memory cells. An acknowledge circuit is coupled to the configuration memory cells. The acknowledge circuit includes a plurality of acknowledge inputs. The configuration memory cells are coupled to selectively set states of the plurality of multiplexers and correspondingly selectively activate inputs of the plurality of acknowledge inputs. A data ready circuit is coupled to at least one multiplexer output of the plurality of multiplexers.

Abstract: An apparatus includes a first output stage and a first input stage of a first single track buffer, as well as a second output stage and a second input stage of a second single track buffer. The second single track buffer is downstream from the first single track buffer. The first output stage and the second input stage are coupled to one another via bidirectional rails. The first output stage and the second input stage in combination provide a first pulse generator.

Abstract: An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.

Abstract: In a multiplier architecture, all stages of a multiplication function are implemented using a uniform array of logic blocks. An exemplary multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each logic block includes a multiply block and a logic circuit driven by the multiply block. The logic circuit is coupled to implement an add function. A first portion of the array is coupled to receive the first and second multiplicand inputs, to provide a partial product bus, and to provide lower bits of the product output. A second portion is coupled to receive the partial product bus from the first portion of the array, and to provide from the partial product bus upper bits of the product output. The multiply blocks may be non-uniform arrays, e.g., logical AND gates and full adders in all but one column, with only logical AND gates in the remaining column.

Abstract: An embodiment of an integrated circuit (IC) is described. This embodiment of the IC includes an interposer; a first die on an interposer, where the first die generates a global signal propagated through the interposer; and a second die on the surface of the interposer and coupled to the global signal. The first die and the second die each is configured to implement a same operating state concurrently in response to the global signal.

Abstract: A method of configuring an integrated circuit (IC) can include receiving configuration data within a master die of the IC. The IC can include the master die and a slave die. A master segment and a slave segment of the configuration data can be determined. The slave segment of the configuration data can be distributed to the slave die of the IC.

Abstract: Circuits for implementing logic replication in self-timed integrated circuits are provided. An exemplary circuit includes first and second copies of a replicated circuit, an input circuit, an output circuit, and a pipelined routing path. The first and second copies each have a self-timed input and a self-timed output. The input circuit provides a self-timed input signal alternately to the self-timed inputs of the first and second copies. The output circuit receives the self-timed output from the first copy and the self-timed output from the second copy, and outputs a selected one of the self-timed outputs based on a value of a self-timed select signal. The pipelined routing path routes the self-timed select signal from the input circuit to the output circuit. The number of pipeline stages in the pipelined routing path can be different from, e.g., less than, the number of stages in both the first and second copies.

Abstract: A programmable integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output multiplexer circuit. The output multiplexer circuit includes a first multiplexer having first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input coupled to an output of another logic block, and a first data output. A second output multiplexer may also have first and second data inputs respectively coupled to the first and second outputs of the logic circuit, a select input coupled to the output of the another logic block, and a second data output. The output multiplexer circuit is programmably coupled, in one of a plurality of operating modes, to provide an output token with the first output of each logic block only when the output multiplexer circuit of the logic block receives tokens indicating valid new data on each of the first, second, and select inputs of the circuit.

Abstract: A cascading output structure for logic blocks in an integrated circuit. An exemplary integrated circuit includes an array of interconnected logic blocks, each including a logic circuit, an output multiplexer, and a select multiplexer. The logic circuit has an input coupled to a logic block input. The output multiplexer has first and second data inputs respectively coupled to first and second outputs of the logic circuit, a select input, and an output coupled to a logic block output. The select multiplexer has a first data input coupled to a cascade select input of the logic block, a second data input, and an output coupled to the select input of the output multiplexer. The output of the select multiplexer is also coupled to a cascade select output of the logic block. The cascade select input of the logic block is coupled to the cascade select output of an adjacent logic block.

Abstract: Integrated circuits having a compute-centric architecture. An integrated circuit may include an array of interconnected substantially similar logic blocks, each including a multiplier circuit and a lookup table circuit. The multiplier circuit has first and second inputs coupled to first and second data inputs of the logic block, and an output, and may include a non-uniform array of sub-circuits. The lookup table circuit has a first input coupled to a third data input of the logic block, a second input coupled to the output of the multiplier circuit, and an output coupled to a data output of the logic block. The multiplier circuits in adjacent logic blocks may be coupled together via a multi-bit partial product bus. Optional storage elements store the first and second inputs and the output of the multiplier circuit, the partial product bus, and the output of the lookup table circuit.

Abstract: Circuits for fanning out data in a self-timed integrated circuit. An exemplary integrated circuit includes a plurality of interconnected logic blocks, each including a logic circuit and an output circuit. The output circuit has a first data input coupled to a first output of the logic circuit, a second data input coupled to a second output of the logic circuit, and a data output coupled to a first output of the logic block. The data output reflects a value on the first data input. The output circuit is programmably coupled, in one of a plurality of operating modes, to provide an output token only when the first data input is accompanied by a first token indicating valid new data on the first data input. The output circuit is further programmably coupled to consume, when the output token is provided, both the first token and a second token accompanying the second data input.

Abstract: Circuits enabling feedback paths in a self-timed integrated circuit. Each of a plurality of interconnected logic blocks includes a logic circuit having first and second outputs, and means for placing, during an initial cycle, a self-timed first data signal on the second output onto a logic block output, and for placing, during subsequent cycles, a self-timed second data signal on a selected one of the first or second outputs onto the logic block output. Initially, an output token is provided only when valid new data is received on the second output and on a select signal. Subsequently, the output token is provided only when either the first output of the logic circuit is selected, and valid new data is received on the first output and on the select signal; or the second output of the logic circuit is selected, and valid new data is received on the first and second outputs and on the select signal.

Abstract: A multi-mode circuit for a self-timed integrated circuit is provided. The multi-mode circuit is programmable to operate in two or more modes, and is coupled to require, in each mode, receipt of a token on at least one of first, second, or third inputs before providing an output token. The multi-mode circuit is further coupled to require tokens on different inputs in at least two different modes. The multi-mode circuit can be an output circuit for a logic block in an integrated circuit including an array of interconnected logic blocks, where each logic block includes a logic circuit and a multi-mode circuit. One input of each multi-mode circuit can be programmably coupled to a select output of a multi-mode circuit in an adjacent logic block. Based on the programmed mode and the tokens received, the circuit routes data between inputs and outputs of the circuit.