Abstract: Some examples described herein relate to redundancy in a multi-chip stacked device. An example described herein is a multi-chip device. The multi-chip device includes a chip stack including vertically stacked chips. Neighboring pairs of the chips are directly connected together. Each of two or more of the chips includes a processing integrated circuit. The chip stack is configurable to operate a subset of functionality of the processing integrated circuits of the two or more of the chips when any portion of the processing integrated circuits is defective.

Abstract: Examples herein describe techniques for forming 3D stacked devices which include a redundant logical layer. The 3D stacked devices include a plurality of semiconductor chips stacked in a vertical direction such that each chip is bonded to a chip above, below, or both in the stack. In one embodiment, each chip is the same—e.g., has the same circuitry arranged in the same configuration in the chip. The 3D stacked device provides a redundant logic layer by dividing the chips into a plurality of slivers which are interconnected by inter-chip bridges. For example, the 3D stacked device may include three stacked chips that are divided into three different slivers where each sliver includes a portion from each of the chips. So long as only one of portions in a sliver is nonfunctional, the inter-chip bridges permit the other portions in the sliver to receive and route data.

Abstract: A system comprises a pair of configurable logic blocks (CLBs) placed adjacent to each other wherein each of the CLBs includes a plurality of configurable logic elements. A plurality sets of inodes are configured to accept signals to and/or from the CLBs, wherein a first set of inodes is positioned to the left of the adjacent CLBs and a second set of inodes is positioned to the right of the adjacent CLBs. A plurality of bnodes are embedded in the middle of the adjacent CLBs, wherein each bnode is configured to establish a first connection between the bnode and one of the first set of inodes on the left of the CLBs and a second connection between the bnode and one of the second set of inodes on the right of the CLBs. Both the first and second routing connections are localized within the pair of adjacent CLBs.

Abstract: A device can include programmable logic circuitry, a processor system coupled to the programmable logic circuitry, and a network-on-chip. The network-on-chip is coupled to the programmable logic circuitry and the processor system. The network-on-chip is programmable to establish user specified data paths communicatively linking a circuit block implemented in the programmable logic circuitry and the processor system. The programmable logic circuitry, the network-on-chip, and the processor system are configured using a platform management controller.

Abstract: Examples herein describe techniques for forming 3D stacked devices which include a redundant logical layer. The 3D stacked devices include a plurality of semiconductor chips stacked in a vertical direction such that each chip is bonded to a chip above, below, or both in the stack. In one embodiment, each chip is the same—e.g., has the same circuitry arranged in the same configuration in the chip. The 3D stacked device provides a redundant logic layer by dividing the chips into a plurality of slivers which are interconnected by inter-chip bridges. For example, the 3D stacked device may include three stacked chips that are divided into three different slivers where each sliver includes a portion from each of the chips. So long as only one of portions in a sliver is nonfunctional, the inter-chip bridges permit the other portions in the sliver to receive and route data.

Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.

Abstract: The disclosed circuit arrangements include a logic circuit, multiple bi-stable circuits, and control circuitry coupled to the bi-stable circuits. Each bi-stable circuit has a data input, a clock input, and an output coupled to the logic circuit. The control circuitry is programmable to selectively connect outputs of the bi-stable circuits or signals at the data inputs of the plurality of bi-stable circuits to inputs of the logic circuit. The control circuitry generates one or more delayed clock signals from the clock signal, and selectively provides one of the one or more delayed clock signals or the clock signal without delay to the clock input of each of the first plurality of bi-stable circuits.

Abstract: The disclosed circuit arrangements include a logic circuit, input register logic coupled to the logic circuit and including a first plurality of bi-stable circuits and a control circuit coupled to the input register logic. The control circuit is configured to generate a plurality of delayed clock signals from an input clock signal. The plurality of delayed clock signals include a first delayed clock signal and a second delayed clock signal. The control circuit selectively provides one or more of the delayed clock signals or the input clock signal to clock inputs of the first plurality of bi-stable circuits and selectively provides one or more of the delayed clock signals or the input clock signal to the logic circuit. The control circuit includes a variable clock delay logic circuit configured to equalize a clock delay to the input register logic with a clock delay to the logic circuit.

Abstract: An apparatus for clock deskew includes: a first delay element configured to receive a clock signal from a clock, wherein the delay element comprises multiple delay lines; a first multiplexer coupled to the multiple delay lines; a sensor configured to sense a voltage, a temperature, or both, and to provide a sensor output based at least on the sensed voltage and/or the sensed temperature; and a converter configured to receive the sensor output, and to generate a converted signal; wherein the first multiplexer is configured to provide a delay line output from one of the multiple delay lines based at least in part on the converted signal.

Abstract: In an example, a semiconductor assembly includes an integrated circuit (IC) die. The IC die includes a first region that includes a programmable fabric; a second region that includes input/output (IO) circuits; and a third region that includes a die seal disposed between the programmable fabric and the IO circuits.

Abstract: In an example, a programmable integrated circuit (IC) includes external contacts configured to interface with a substrate and a plurality of configurable logic elements (CLEs) distributed across a programmable fabric. The programmable IC further includes interconnect circuits disposed between the plurality of CLEs and the external contacts. A plurality of the interconnect circuits is disposed in the plurality of CLEs.

Abstract: In an example, a LUT for a programmable integrated circuit (IC) includes a plurality of input terminals, and a cascading input coupled to at least one other LUT in the programmable IC. The LUT further includes LUT logic having a plurality of LUTs each coupled to a common set of the input terminals. The LUT further includes a plurality of multiplexers having inputs coupled to outputs of the plurality of LUTs, and an output multiplexer having inputs coupled to outputs of the plurality of multiplexers. The LUT further includes a plurality of cascading multiplexers each having an output coupled to a control input of a respective one of the plurality of multiplexers, each of the plurality of cascading multiplexers comprising a plurality of inputs, at least one of the plurality of inputs coupled to the cascading input.

Abstract: A circuit for generating clock signals enabling the latching of data is described. The circuit comprises a pulse generator coupled to receive an input clock signal at an input and to generate an output clock signal at an output; a latch circuit coupled to receive the output clock signal; and a pulse shaping circuit coupled to receive a feedback signal; wherein a pulse width of the output clock signal is determined by the feedback signal and the input signal coupled to the pulse generator. A method of generating clock signals enabling the latching of data is also described.

Abstract: An interconnect multiplexer comprises a plurality of CMOS pass gates of a first multiplexer stage coupled to receive data to be output by the interconnect multiplexer; an output inverter coupled to the outputs of the plurality of CMOS pass gates, wherein an output of the output inverter is an output of the interconnect multiplexer; and a plurality of memory elements coupled to the plurality of CMOS pass gates; wherein inputs to the plurality of CMOS pass gates are pulled to a common potential during a startup mode. A method of reducing contention currents in an integrated circuit is also disclosed.

Abstract: An integrated circuit includes: a voltage rail; voltage control circuitry coupled to the voltage rail; and a circuit block coupled to the voltage control circuitry; wherein the voltage control circuitry is selectively configurable to operate the circuit block in at least a first mode of operation and a second mode of operation; wherein in the first mode of operation, the circuit block receives a voltage that is substantially the same as a voltage of the voltage rail; and wherein in the second mode of operation, the circuit block receives a voltage that is less than the voltage of the voltage rail by a threshold voltage.

Abstract: In an example, a configurable logic element for a programmable integrated circuit (IC) includes a first lookup-table (LUT) including first inputs and first outputs, and first sum logic and first carry logic coupled between the first inputs and the first outputs; a second LUT including second inputs and second outputs, and second sum logic coupled between the second inputs and the second outputs; and first and second cascade multiplexers respectively coupled to the first and second LUTs, an input of the second cascade multiplexer coupled to an output of the first carry logic in the first LUT.

Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.

Abstract: A signed multiplier circuit includes a two-dimensional array of substantially similar logic blocks. Each of the logic blocks is programmable to implement any of four multiply functions of first and second inputs, in which: the first and second inputs are both signed; the first and second inputs are both unsigned; the first input is signed and the second input is unsigned; and the first input is unsigned and the second input is signed. Each logic block includes rows and columns of sub-circuits, e.g., logical AND gates and full adders. One row and one column of each logic block include a programmably invertible AND gate, with the row and column being independently controlled. The ability to program the logic block to perform all four of these functions enables the combination of rows and columns of the logic blocks to build large signed multipliers of virtually any size.

Abstract: A circuit for controlling power within an integrated circuit comprises a plurality of circuit blocks; a global control signal routed within the integrated circuit; and a plurality of power control blocks. Each power control block is coupled to a corresponding circuit block of the plurality of circuit bocks and has a first input coupled to receive a reference voltage and a second input coupled to receive the global control signal. The global control signal enables, for each circuit block, the coupling of the reference voltage to the corresponding circuit block. A method of controlling power within an integrated circuit is also disclosed.

Abstract: A system includes: an initial clock region; a first adjacent clock region adjacent to the initial clock region; a spine coupled to receive a clock signal from a clock; and a first phase detector coupled to detect a difference in phase between the initial clock region and the first adjacent clock region. The initial clock region comprises an initial delay element coupled to the spine and to the first phase detector.