Abstract: Low resistance field-effect transistors and methods of manufacturing the same are disclosed herein. An example field-effect transistor disclosed herein includes a substrate and a stack above the substrate. The stack includes an insulator and a gate electrode. The example field-effect transistor includes a semiconductor material layer in a cavity in the stack. In the example field-effect transistor, a region of the semiconductor material layer proximate to the insulator is doped with a material of the insulator.

Abstract: Transistor structures with a deposited channel semiconductor material may have a vertical structure that includes a gate dielectric material that is localized to a sidewall of a gate electrode material layer. With localized gate dielectric material threshold voltage variation across a plurality of vertical transistor structures, such as a NAND flash memory string, may be reduced. A via may be formed through a material stack, exposing a sidewall of the gate electrode material layer and sidewalls of the dielectric material layers. A sidewall of the gate electrode material layer may be recessed selectively from the sidewalls of the dielectric material layers. A gate dielectric material, such as a ferroelectric material, may be selectively deposited upon the recessed gate electrode material layer, for example at least partially backfilling the recess. A semiconductor material may be deposited on sidewalls of the dielectric material layers and on the localized gate dielectric material.

Abstract: The present disclosure relates to the fabrication of spin transfer torque memory devices, wherein a magnetic tunnel junction of the spin transfer torque memory device is formed with Heusler alloys as the fixed and free magnetic layers and a tunnel barrier layer disposed between and abutting the fixed Heusler magnetic layer and the free Heusler magnetic layer, wherein the tunnel barrier layer is lattice matched to the free Heusler magnetic layer. In one embodiment, the tunnel barrier layer may be a strontium titanate layer.

Abstract: A mobile fuel monitoring system (MMU) is disclosed. The fuel monitoring system may be skid mounted and is configured to monitor fuel transfers between a fuel source and a vessel, such as a ship. The disclosed MMU is a stand-alone, self-contained unit that can be easily moved from place to place. The MMU is configured to monitor and remotely report custody transfers of fuel performed at any location. Parameters of the fuel transfer operation, such as the amount of fuel transferred, the flow rate, the fuel density, and fuel temperature can be monitored and alarms may be issued if any of the parameters are out of specification. The parameter values may be transmitted to a remote location, for example, via a satellite link.

Abstract: A welding-type system includes a power supply configured to control preheating of an electrode wire. A controller is configured to receive a plurality of power values corresponding to a power output of the power supply and calculate an arc power value corresponding to an arc condition at the preheated electrode wire based on a rate of change of the plurality of power values. A target power output value is determined based on the calculated arc power value, and the power output is adjusted based on the determined target power value.

Abstract: Transistor structures with a deposited channel semiconductor material may have a vertical structure that includes a gate dielectric material that is localized to a sidewall of a gate electrode material layer. With localized gate dielectric material threshold voltage variation across a plurality of vertical transistor structures, such as a NAND flash memtory string, may be reduced. A via may be formed through a material stack, exposing a sidewall of the gate electrode material layer and sidewalls of the dielectric material layers. A sidewall of the gate electrode material layer may be recessed selectively from the sidewalls of the dielectric material layers. A gate dielectric material, such as a ferroelectric material, may be selectively deposited upon the recessed gate electrode material layer, for example at least partially backfilling the recess. A semiconductor material may be deposited on sidewalls of the dielectric material layers and on the localized gate dielectric material.

Abstract: A welding-type system includes a power supply configured to control preheating of an electrode wire. A controller is configured to receive a plurality of power values corresponding to a power output of the power supply and calculate an arc power value corresponding to an arc condition at the preheated electrode wire based on a rate of change of the plurality of power values. A target power output value is determined based on the calculated arc power value, and the power output is adjusted based on the determined target power value.

Abstract: IC device including back-end-of-line (BEOL) transistors with crystalline channel material. A BEOL crystalline seed may be formed over a dielectric layer that has been planarized over a front-end-of-line (FEOL) transistor level that employs a monocrystalline substrate semiconductor. The BEOL crystalline seed may be epitaxial to the substrate semiconductor, or may have crystallinity independent of that of the substrate semiconductor. The BEOL crystalline seed may comprise a first material having a higher melt temperature than a melt material formed over the seed and over the dielectric layer. Through rapid melt growth, the melt material may be heated to a temperature sufficient to transition from an as-deposited state to a more crystalline state that is derived from, and therefore associated with, the BEOL crystalline seed. A BEOL transistor may then be fabricated from the crystallized material.

Abstract: Embodiments herein describe techniques for a semiconductor device including a SRAM device having multiple SRAM memory cells, and a capacitor coupled to the SRAM device. The capacitor includes a first plate, a second plate, and a capacitor dielectric layer between the first plate and the second plate. The capacitor is to supply power to the multiple SRAM memory cells of the SRAM device in parallel for a period of time. Other embodiments may be described and/or claimed.

Abstract: A solid oxide fuel cell capable of directly utilizing hydrocarbons as a fuel source at operating temperatures between 200° C. and 500° C. The anode, electrolyte, and cathode of the solid oxide fuel cell can include technologies for improved operation at temperatures between 200° C. and 500° C. The anode can include technologies for improved direct utilization of hydrocarbon fuel sources.

Abstract: Low resistance field-effect transistors and methods of manufacturing the same are disclosed herein. An example field-effect transistor disclosed herein includes a substrate and a stack above the substrate. The stack includes an insulator and a gate electrode. The example field-effect transistor includes a semiconductor material layer in a cavity in the stack. In the example field-effect transistor, a region of the semiconductor material layer proximate to the insulator is doped with a material of the insulator.

Abstract: Embodiments herein describe techniques for a semiconductor device including a semiconductor substrate, a first device of a first wafer, and a second device at back end of a second wafer, where the first device is bonded with the second device. A first metal electrode of the first device within a first dielectric layer is coupled to an n-type oxide TFT having a channel layer that includes an oxide semiconductor material. A second metal electrode of the second device within a second dielectric layer is coupled to p-type organic TFT having a channel layer that includes an organic material. The first dielectric layer is bonded to the second dielectric layer, and the first metal electrode is bonded to the second metal electrode. The n-type oxide TFT and the p-type organic TFT form a symmetrical pair of transistors of a CMOS circuit. Other embodiments may be described and/or claimed.

Abstract: A transistor is disclosed. The transistor includes a p-type region, an intrinsic region coupled to the p-type region, an n-type region coupled to the intrinsic region, and a gate electrode above the intrinsic region. The ferroelectric material is on a bottom, a first side and a second side of the gate electrode, and above the intrinsic region.

Abstract: A memory cell is disclosed. The memory cell includes a word line contact, a cylindrical electrode having a top region and a bottom region, and RRAM material covering the surface of the cylindrical electrode from the top region to the bottom region. A select transistor contact is coupled to the bottom region of the cylindrical electrode.

Abstract: Embodiments herein describe techniques for a thin-film transistor (TFT), which may include a substrate and a transistor above the substrate. The transistor includes a channel layer above the substrate, a gate dielectric layer adjacent to the channel layer, and a gate electrode separated from the channel layer by the gate dielectric layer. The gate dielectric layer includes a non-linear gate dielectric material. The gate electrode, the channel layer, and the gate dielectric layer form a non-linear capacitor. Other embodiments may be described and/or claimed.

Abstract: Embodiments disclosed herein comprise a ferroelectric material layer and methods of forming such materials. In an embodiment, the ferroelectric material layer comprises hafnium oxide with an orthorhombic phase. In an embodiment, the ferroelectric material layer may also comprise trace elements of a working gas. Additional embodiments may comprise: a semiconductor channel, a source region on a first end of the semiconductor channel, a drain region on a second end of the semiconductor channel, a gate electrode over the semiconductor channel, and a gate dielectric between the gate electrode and the semiconductor channel. In an embodiment, the gate dielectric includes a ferroelectric hafnium oxide. In an embodiment, the hafnium oxide is substantially free from dopants.

Abstract: A MTJ device includes a free (storage) magnet and fixed (reference) magnet between first and second electrodes, and a programmable booster between the free magnet and one of the electrodes. The booster comprises a magnetic material layer. The booster may further comprise an interface layer that supports the formation of a skyrmion spin texture, or a stable ferromagnetic domain, within the magnetic material layer. A programming current between two circuit nodes may be employed to set a position of the skyrmion or magnetic domain within the magnetic material layer to be more proximal to, or more distal from, the free magnet. The position of the skyrmion or magnetic domain to the MTJ may modulate TMR ratio of the MTJ device. The TMR ratio modulation may be employed to discern more than two states of the MTJ device. Such a multi-level device may, for example, be employed to store 2 bits/cell.

Abstract: Integrated circuits including 3D memory structures are disclosed. Air-gaps are purposefully introduced between word lines. The word lines may be horizontal or vertical.

Abstract: A backend electrostatic discharge (ESD) diode device structure is presented comprising: a first structure comprising a first material, wherein the first material includes metal; a second structure adjacent to the first structure, wherein the second structure comprises a second material, wherein the second material includes a semiconductor or an oxide; and a third structure adjacent to the second structure, wherein the third structure comprises of the first material, wherein the second structure is between the first and third structures. Other embodiments are also disclosed and claimed.

Abstract: An apparatus comprises a magnetic tunnel junction (MTJ) including a free magnetic layer, a fixed magnetic layer, and a tunnel barrier between the free and fixed layers, the tunnel barrier directly contacting a first side of the free layer, a capping layer contacting the second side of the free magnetic layer and boron absorption layer positioned a fixed distance above the capping layer.