Abstract: The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.

Abstract: A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to stacked gate transistors and methods of manufacture. The structure includes a stacked gate structure having a plurality of transistors with at least one floating node and at least one node to either ground or a supply voltage, and a contact to either of the ground or supply voltage and the at least one floating node being devoid of any contact.

Abstract: A dielectric fill layer within source/drain metallization trenches limits the depth of an inlaid metallization layer over isolation regions of a semiconductor device. The modified geometry decreases parasitic capacitance as well as the propensity for electrical short circuits between the source/drain metallization and adjacent conductive structures, which improves device reliability and performance.

Abstract: A dummy gate structure straddling at least one semiconductor fin is formed on a substrate. Active semiconductor regions and raised active semiconductor regions may be formed. A planarization dielectric layer is formed over the at least one semiconductor fin, and the dummy gate structure is removed to provide a gate cavity. Electrical dopants in the channel region can be removed by outgassing during an anneal, thereby lowering the concentration of the electrical dopants in the channel region. Alternately or additionally, carbon can be implanted into the channel region to deactivate remaining electrical dopants in the channel region. The threshold voltage of the field effect transistor can be effectively controlled by the reduction of active electrical dopants in the channel region. A replacement gate electrode can be subsequently formed in the gate cavity.

Abstract: A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.

Abstract: A self-aligned active region block mask is used to pattern and define a plurality of semiconductor fins as well as attendant shallow trench isolation (STI) structures. The block mask, a portion of which comprises a patterned fin hard mask, permits decoupling of inner and outer fin etch processes, as well as independent optimization of inner fin and outer fin dielectric properties. The fin-forming method also forestalls the creation of isolated, free-standing fins, which decreases the likelihood of mechanical damage to the fins during processing.

Abstract: A fin cut process cuts semiconductor fins after forming sacrificial gate structures that overlie portions of the fins. Selected gate structures are removed to form openings and exposed portions of the fins within the openings are etched. An isolation dielectric layer is deposited into the openings and between end portions of the cut fins. The process enables a single sacrificial gate structure to define the spacing between two active regions on dissimilar electrical nets.

Abstract: A fin cut process cuts semiconductor fins after forming sacrificial gate structures that overlie portions of the fins. Selected gate structures are removed to form openings and exposed portions of the fins within the openings are etched. An isolation dielectric layer is deposited into the openings and between end portions of the cut fins. The process enables a single sacrificial gate structure to define the spacing between two active regions on dissimilar electrical nets.

Abstract: Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.

Abstract: Aspects of the present disclosure include integrated circuit (IC) structure and methods for increasing a pitch between gates. Methods according to the present disclosure can include: providing an IC structure including: a first gate structure and a second gate structure each positioned on a substrate, a dummy gate positioned between the first and second gate structures, and forming a mask over the first and second gate structures; and selectively etching the dummy gate from the IC structure to expose a portion of the substrate underneath the dummy gate of the IC structure, without affecting the first and second gate structures.

Abstract: A method of making a semiconductor device includes disposing a mask on a substrate; etching the mask to form an opening in the mask; etching a trench in the substrate beneath the opening in the mask; and implanting a dopant in an area of the substrate beneath the opening of the mask, the dopant capable of gettering mobile ions that can contaminate the substrate; wherein the dopant extends through the substrate from a sidewall of the trench and an endwall of the trench.

Abstract: A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the plurality of fins remaining exposed. Spacers are formed on opposite sidewalls of the second portion of the plurality of fins. The second portion of the plurality fins is removed to form a trench between the spacers. An epitaxial layer is formed in the trench. The spacers on opposite sides of the epitaxial layer constrain lateral growth of the epitaxial layer.

Abstract: A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the plurality of fins remaining exposed. Spacers are formed on opposite sidewalls of the second portion of the plurality of fins. The second portion of the plurality fins is removed to form a trench between the spacers. An epitaxial layer is formed in the trench. The spacers on opposite sides of the epitaxial layer constrain lateral growth of the epitaxial layer.

Abstract: A method for producing a semiconductor structure, as well as a semiconductor structure, that uses a partial removal of an insulating layer around a semiconductor fin, and subsequently epitaxially growing an additional semiconductor material in the exposed regions, while maintaining the shape of the fin with the insulating layer.

Abstract: A method includes forming a plurality of fins on a substrate, a gate is formed over a first portion of the plurality of fins with a second portion of the plurality of fins remaining exposed. Spacers are formed on opposite sidewalls of the second portion of the plurality of fins. The second portion of the plurality fins is removed to form a trench between the spacers. An epitaxial layer is formed in the trench. The spacers on opposite sides of the epitaxial layer constrain lateral growth of the epitaxial layer.

Abstract: A method includes forming a plurality of fins on a substrate, conformally depositing a nitride liner above and in direct contact with the plurality of fins and the substrate, removing a top portion of the nitride liner above the plurality of fins to expose a top surface of the plurality of fins, forming a gate over a first portion of the plurality of fins, a second portion of the plurality of fins remains exposed, forming spacers on opposite sidewalls of the nitride liner on the second portion of the plurality of fins, removing the second portion of the plurality of fins to form a trench between opposing sidewalls of the nitride liner, and forming an epitaxial layer in the trench, the lateral growth of the epitaxial layer is constrained by the nitride liner to form constrained source-drain regions.

Abstract: A semiconductor device such as a FinFET includes a plurality of fins formed upon a substrate and a gate covering a portion of the fins. Diamond-shaped volumes are formed on the sidewalls of the fins by epitaxial growth which may be limited to avoid merging of the volumes or where the epitaxy volumes have merged. Because of the difficulties in managing merging of the diamond-shaped volumes, a controlled merger of the diamond-shaped volumes includes depositing an amorphous semiconductor material upon the diamond-shaped volumes and a crystallization process to crystallize the deposited semiconductor material on the diamond-shaped volumes to fabricate controllable and uniformly merged source drain.

Abstract: Structures and methods for deep trench capacitor connections are disclosed. The structure includes a reduced diameter top portion of the capacitor conductor. This increases the effective spacing between neighboring deep trench capacitors. Silicide or additional polysilicon are then deposited to complete the connection between the deep trench capacitor and a neighboring transistor.