Patents by Inventor Bruce E. Gnade
Bruce E. Gnade has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11296140Abstract: A thin film radiation detection device includes a photosensitive p-n diode, a polysilicon thin film transistor (TFT), a radiation detection layer, and a substrate. The photosensitive p-n diode and the TFT are formed on the substrate. The radiation detection layer is formed above the substrate and receives multiple radiations. The photosensitive p-n diode receives a conversion output signal from the radiation detection layer and generates a detector signal. The TFT generates an amplified signal based on the detector signal.Type: GrantFiled: April 13, 2018Date of Patent: April 5, 2022Assignee: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: Jesus I. Mejia-Silva, Manuel Quevedo-Lopez, Bruce E. Gnade, Carlos Hugo Avila Avendano, Bhabendra K. Pradhan
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Publication number: 20200292719Abstract: A system for detecting radiations includes an array of detectors for receiving the radiations and an integrated circuit (IC). Each detector detects a specific type of radiation and generates a corresponding detector output signal. The IC receives the corresponding detector output signal from each detector and generates an output signal that is indicative of detecting the radiations. The array of detectors is implemented using at least one of a silicon technology and a thin film technology. The IC is implemented using at least one of a complementary metal oxide semiconductor (CMOS) technology and the thin film technology.Type: ApplicationFiled: March 17, 2017Publication date: September 17, 2020Inventors: Manuel Quevedo-Lopez, Jesus I. Mejia Silva, Bhabendra K. Pradhan, Bruce E. Gnade
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Publication number: 20200127038Abstract: A thin film radiation detection device includes a photosensitive p-n diode, a thin film transistor (TFT), a radiation detection layer, and a substrate. The photosensitive p-n diode and the TFT are formed on the substrate. The radiation detection layer is formed above the substrate and receives multiple radiations. The photosensitive p-n diode receives a conversion output signal from the radiation detection layer and generates a detector signal. The TFT generates an amplified signal based on the detector signal.Type: ApplicationFiled: April 13, 2018Publication date: April 23, 2020Inventors: Jesus I. Mejia-Silva, Manuel Quevedo-Lopez, Bruce E. Gnade, Carlos Hugo Avila Avendano, Bhabendra K. Pradhan
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Publication number: 20160322559Abstract: The claimed invention is directed to integrated energy-harvesting piezoelectric cantilevers. The cantilevers are fabricated using sol-gel processing using a sacrificial poly-Si seeding layer. Improvements in film microstructure and electrical properties are realized by introducing a poly-Si seeding layer and by optimizing the poling process.Type: ApplicationFiled: July 10, 2016Publication date: November 3, 2016Inventors: Erika Fuentes-Fernandez, Pradeep Shah, Wardia Mechtaly-Debray, Bruce E. Gnade
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Patent number: 9388041Abstract: The claimed invention is directed to integrated energy-harvesting piezoelectric cantilevers. The cantilevers are fabricated using sol-gel processing using a sacrificial poly-Si seeding layer. Improvements in film microstructure and electrical properties are realized by introducing a poly-Si seeding layer and by optimizing the poling process.Type: GrantFiled: December 2, 2013Date of Patent: July 12, 2016Assignees: The Board of Regents of the University of Texas System, Texas Micropower Inc.Inventors: Erika Fuentes-Fernandez, Pradeep Shah, Wardia Mechtaly-Debray, Bruce E. Gnade
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Publication number: 20140087509Abstract: The claimed invention is directed to integrated energy-harvesting piezoelectric cantilevers. The cantilevers are fabricated using sol-gel processing using a sacrificial poly-Si seeding layer. Improvements in film microstructure and electrical properties are realized by introducing a poly-Si seeding layer and by optimizing the poling process.Type: ApplicationFiled: December 2, 2013Publication date: March 27, 2014Applicants: Texas Micropower, Inc., The Board of Regents of the University of Texas SystemInventors: Erika Fuentes-Fernandez, Pradeep Shah, Wardia Mechtaly-Debray, Bruce E. Gnade
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Patent number: 8633634Abstract: The claimed invention is directed to integrated energy-harvesting piezoelectric cantilevers. The cantilevers are fabricated using sol-gel processing using a sacrificial poly-Si seeding layer. Improvements in film microstructure and electrical properties are realized by introducing a poly-Si seeding layer and by optimizing the poling process.Type: GrantFiled: November 17, 2012Date of Patent: January 21, 2014Assignees: The Board of Regents of the University of Texas System, Texas Micropower, Inc.Inventors: Erika Fuentes-Fernandez, Pradeep Shah, Wardia Mechtaly-Debray, Bruce E. Gnade
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Publication number: 20090136594Abstract: The present invention includes compositions, methods, devices and kits for magnetizing a biological particle by contacting a biological particle with a ferrous or magnetic particle that is able to specifically bind the biological particle and reacting the biological particle with the ferrous or magnetic particle under physiological conditions, wherein the ferrous or magnetic particle causes the biological particle to become attractable magnetically.Type: ApplicationFiled: November 26, 2008Publication date: May 28, 2009Applicant: BOARD OF REGENTS, THE UNIVERSITY OF TEXAS SYSTEMInventors: Stacey L. McLeroy, Bruce E. Gnade, Jeffrey A. Cadeddu, Margaret Pearle
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Patent number: 7288171Abstract: A method is provided, the method comprising operating a field emitter array (FEA) to generate at least one of a high electric field and a high electron flux, and exposing the field emitter array (FEA) to at least one gas. The method further comprises generating at least one radical species from the at least one gas exposed to the at least one of the high electric field and the high electron flux.Type: GrantFiled: January 18, 2002Date of Patent: October 30, 2007Assignee: University of North TexasInventors: Bruce E. Gnade, Robert M. Wallace
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Patent number: 6933235Abstract: A method of processing a substrate is disclosed. The method includes depositing a dielectric layer having a metal oxide on a substrate. A portion of the dielectric layer is removed to form a dielectric structure, thereby exposing a surface of the substrate. For example, the dielectric layer may be patterned using standard photolithographic techniques and etching. An oxide layer is then formed on the exposed surface of the substrate. The oxide layer may be formed using ozone that is generated using ultraviolet radiation. After the oxide layer is formed, it is removed using an etching process.Type: GrantFiled: November 21, 2002Date of Patent: August 23, 2005Assignee: The Regents of the University of North TexasInventors: Manuel A. Quevedo-Lopez, Robert M. Wallace, Mohamed El Bouanani, Bruce E. Gnade
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Patent number: 6784507Abstract: CMOS and BiCMOS structures with a silicate-germanate gate dielectric on SiGe PMOS areas and Si NMOS areas plus HBTs with Si—SiGe emitter-base junctions.Type: GrantFiled: September 27, 2002Date of Patent: August 31, 2004Assignee: Texas Instruments IncorporatedInventors: Robert M. Wallace, Bruce E. Gnade
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Publication number: 20040102009Abstract: A method of processing a substrate is disclosed. The method includes depositing a dielectric layer having a metal oxide on a substrate. A portion of the dielectric layer is removed to form a dielectric structure, thereby exposing a surface of the substrate. For example, the dielectric layer may be patterned using standard photolithographic techniques and etching. An oxide layer is then formed on the exposed surface of the substrate. The oxide layer may be formed using ozone that is generated using ultraviolet radiation. After the oxide layer is formed, it is removed using an etching process.Type: ApplicationFiled: November 21, 2002Publication date: May 27, 2004Applicant: REGENTS OF THE UNIVERSITY OF NORTH TEXASInventors: Manuel A. Quevedo-Lopez, Robert M. Wallace, Mohamed El Bouanani, Bruce E. Gnade
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Patent number: 6645878Abstract: This invention has enabled a new, simple thin film nanoporous dielectric fabrication method. In general, this invention uses glycerol, or another low volatility compound, as a solvent. This new method allows thin film aerogels/low density xerogels to be made without supercritical drying, freeze drying, or a surface modification step before drying. Thus, this invention allows production of nanoporous dielectrics at room temperature and atmospheric pressure, without a separate surface modification step. Although this new method allows fabrication of aerogels without substantial pore collapse during drying, there may be some permanent shrinkage during aging and/or drying. This invention allows controlled porosity thin film nanoporous aerogels to be deposited, gelled, aged, and dried without atmospheric controls.Type: GrantFiled: April 30, 2002Date of Patent: November 11, 2003Assignee: Texas Instruments IncorporatedInventors: Douglas M. Smith, Gregory P. Johnston, William C. Ackerman, Richard A. Stoltz, Alok Maskara, Teresa Ramos, Shin-Puu Jeng, Bruce E. Gnade
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Publication number: 20030062586Abstract: CMOS and BiCMOS structures with a silicate-germanate gate dielectric on SiGe PMOS areas and Si NMOS areas plus HBTs with Si—SiGe emitter-base junctions.Type: ApplicationFiled: September 27, 2002Publication date: April 3, 2003Inventors: Robert M. Wallace, Bruce E. Gnade
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Publication number: 20030022524Abstract: This invention has enabled a new, simple thin film nanoporous dielectric fabrication method. In general, this invention uses glycerol, or another low volatility compound, as a solvent. This new method allows thin film aerogels/low density xerogels to be made without supercritical drying, freeze drying, or a surface modification step before drying. Prior art aerogels have required at least one of these steps to prevent substantial pore collapse during drying. Thus, this invention allows production of nanoporous dielectrics at room temperature and atmospheric pressure, without a separate surface modification step. In general, this new method is compatible with most prior art aerogel techniques. Although this new method allows fabrication of aerogels without substantial pore collapse during drying, there may be some permanent shrinkage during aging and/or drying. This invention allows controlled porosity thin film nanoporous aerogels to be deposited, gelled, aged, and dried without atmospheric controls.Type: ApplicationFiled: April 30, 2002Publication date: January 30, 2003Inventors: Douglas M. Smith, Gregory P. Johnston, William C. Ackerman, Richard A. Stoltz, Alok Maskara, Teresa Ramos, Shin-Puu Jeng, Bruce E. Gnade
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Patent number: 6437007Abstract: This invention pertains generally to precursors and deposition methods suited to aerogel thin film fabrication. An aerogel precursor sol which contains an oligomerized metal alkoxide (such as TEOS), a high vapor pressure solvent (such as ethanol) and a low vapor pressure solvent (such as water and 1-butanol) is disclosed. By a method according to the present invention, such a precursor sol is applied as a thin film to a semiconductor wafer, and the high vapor pressure solvent is allowed to evaporate while evaporation of the low vapor pressure solvent is limited, preferably by controlling the atmosphere adjacent to the wafer. The reduced sol is then allowed to gel at a concentration determined by the ratio of metal alkoxide to low vapor pressure solvent. One advantage of the present invention is that it provides a stable, spinnable sol for setting film thickness and providing good planarity and gap fill for patterned wafers.Type: GrantFiled: April 14, 2000Date of Patent: August 20, 2002Assignee: Texas Instruments IncorporatedInventors: Douglas M. Smith, Gregory P. Johnston, William C. Ackerman, Shin-Puu Jeng, Bruce E. Gnade
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Patent number: 6419742Abstract: A method of forming lattice matched single crystal wide bandgap II-VI compound semiconductor films over a silicon substrate includes first cleaning (10) the silicon substrate. A passivation layer is formed (18), which may comprise arsenic, germanium, or CaF2, among others. The lattice matched layer is then grown (26) on the passivation layer.Type: GrantFiled: November 15, 1994Date of Patent: July 16, 2002Assignees: Texas Instruments Incorporated, Texas A&M University SystemInventors: Wiley P. Kirk, Joe X. Zhou, Bruce E. Gnade, Chih-Chen Cho
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Patent number: 6380105Abstract: This invention has enabled a new, simple thin film nanoporous dielectric fabrication method. In general, this invention uses glycerol, or another low volatility compound, as a solvent. This new method allows thin film aerogels/low density xerogels to be made without supercritical drying, freeze drying, or a surface modification step before drying. Thus, this invention allows production of nanoporous dielectrics at room temperature and atmospheric pressure, without a separate surface modification step. Although this new method allows fabrication of aerogels without substantial pore collapse during drying, there may be some permanent shrinkage during aging and/or drying. This invention allows controlled porosity thin film nanoporous aerogels to be deposited, gelled, aged, and dried without atmospheric controls.Type: GrantFiled: June 2, 1999Date of Patent: April 30, 2002Assignee: Texas Instruments IncorporatedInventors: Douglas M. Smith, Gregory P. Johnston, William C. Ackerman, Richard A. Stoltz, Alok Maskara, Teresa Ramos, Shin-Puu Jeng, Bruce E. Gnade
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Publication number: 20020025626Abstract: This invention pertains generally to the integration of dielectrics with integrated circuits, and more particularly to reaction barriers between high-k dielectrics and an underlying Group IV semiconductor layer. Applications for high permittivity memory cells and gate dielectrics are disclosed. This method has steps of providing a partially completed integrated circuit having a semiconductor layer substantially comprising silicon, where the layer has an exposed face. The method also includes forming an ultra-thin SiC reaction barrier at the exposed face, and depositing a high permittivity storage dielectric on the SiC reaction barrier. Typically, the SiC reaction barrier is less than 25 Å thick, preferably one or two monolayers of SiC.Type: ApplicationFiled: August 27, 2001Publication date: February 28, 2002Inventors: Sunil Hattangady, Robert M. Wallace, Bruce E. Gnade, Yasutoshi Okuno
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Patent number: 6335238Abstract: This invention pertains generally to the integration of dielectrics with integrated circuits, and more particularly to reaction barriers between high-k dielectrics and an underlying Group IV semiconductor layer. Applications for high permittivity memory cells and gate dielectrics are disclosed. This method has steps of providing a partially completed integrated circuit having a semiconductor layer substantially comprising silicon, where the layer has an exposed face. The method also includes forming an ultra-thin SiC reaction barrier at the exposed face, and depositing a high permittivity storage dielectric on the SiC reaction barrier. Typically, the SiC reaction barrier is less then 25 Å thick, preferably one or two monolayers of SiC.Type: GrantFiled: May 5, 1998Date of Patent: January 1, 2002Assignee: Texas Instruments IncorporatedInventors: Sunil V. Hanttangady, Robert M. Wallace, Bruce E. Gnade, Yasutoshi Okuno