Abstract: This invention provides an improved porous structure for semiconductor devices and a process for making the same. This process may be applied to an existing porous structure 28, which may be deposited, for example, between patterned conductors 24. The process may include baking the structure in a reducing atmosphere, preferably a forming gas, to dehydroxylate the pore surfaces. The process may include baking the structure in a halogen-containing atmosphere to bond halogens to the pore surfaces. It has been found that a porous structure treated in such a manner generally exhibits improved dielectric properties relative to an untreated sample.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying and gelling one or more solutions between and over conductors 24 and drying the wet gel to create at least porous dielectric sublayers 28 and 29. By varying the composition of the solutions, gelling conditions, drying temperature, composition of the solvents in the wet gel, or a combination of these approaches, the porosity of the sublayers may be tailored individually. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A grooved anode plate 40 for use in a field emission flat panel display device comprises a transparent planar substrate 42 having a plurality of electrically conductive, parallel stripes 46 comprising the anode electrode of the device, which are covered by phosphors 48.sub.R, 48.sub.G and 48.sub.B. In one embodiment, grooves 50, having generally straight sidewalls, are formed in the upper surface of planar substrate 42 at the interstices of conductors 46. In a second embodiment, grooves 50', which provide a substantial undercutting of the material of substrate 42' adjacent the edges of conductors 46', are formed in the upper surface of planar substrate 42' at the interstices of conductors 46'. A substantially opaque, electrically insulating material 52 is affixed to substrate 42 in the grooves 50 formed between conductors 46, acting as a barrier to the passage of ambient light into and out of the device.

Abstract: This invention provides a semiconductor device and process for making the same with dramatically reduced capacitance between adjacent conductors and an interlayer dielectric construction which emphasizes mechanical strength, etch compatibility, and good heat transfer. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric and provide mechanical strength, heat transfer, and a solid layer for via etch. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: A ferroelectric integrated circuit is provided in which a first layer of conducting lines (14) is formed over an insulating base layer (10). A first ferroelectric layer (16) is formed overlying the first layer of conducting lines (14). A second layer of conducting lines (18) is formed overlying the first ferroelectric layer (16) with each of the conducting lines of the second layer of conducting lines (18) being substantially perpendicular to the conducting lines of the first layer of conducting lines (14). Potentials placed on selected conducting lines in the first and second layers of conducting lines (14 and 18) polarize areas of the first ferroelectric layer (16) between intersections of the selected conducting lines. Multiple layers may be stacked to form a three-dimensional ferroelectric integrated circuit.

Abstract: A semiconductor device and process for making the same are disclosed which use porous dielectric materials to reduce capacitance between conductors, while allowing conventional photolithography and metal techniques and materials to be used in fabrication. In one structure, patterned conductors 18 are provided on an interlayer dielectric 10, with a substrate encapsulation layer 32 deposited conformally over this structure. A layer of porous dielectric material 22 (e.g. dried SiO.sub.2 gel) is then deposited to substantially fill the gaps between and also cover the conductors. A substantially solid cap layer 24 of a material such as SiO.sub.2 is then deposited, followed by a photolithography step to define via locations. Vias are etched through the cap layer, and then through the porous dielectric.

Abstract: This invention provides a process for making a semiconductor device with reduced capacitance between adjacent conductors. This process can include applying a solution between conductors 24, and then gelling, surface modifying, and drying the solution to form an extremely porous dielectric layer 28. A non-porous dielectric layer 30 may be formed over porous layer 28, which may complete an interlayer dielectric. A novel process for creating the porous dielectric layer is disclosed, which can be completed at vacuum or ambient pressures, yet results in porosity, pore size, and shrinkage of the dielectric during drying comparable to that previously attainable only by drying gels at supercritical pressure.

Abstract: An anode plate 40 for use in a field emission flat panel display device comprises a transparent planar substrate 42 having a plurality of electrically conductive, parallel stripes 46 comprising the anode electrode of the device, which are covered by phosphors 48.sub.R, 48.sub.G and 48.sub.B, and a gettering material 52 in the interstices of the stripes 46. The gettering material 52 is preferably selected from among zirconium-vanadium-iron and barium. The getter 52 may be thermally reactivated by passing a current through it at selected times, or by electron bombardment from microtips on the emitter substrate. The getter 52 may be formed on a substantially opaque, electrically insulating material 50 affixed to substrate 42 in the spaces formed between conductors 46, which acts as a barrier to the passage of ambient light into and out of the device. Methods of fabricating the getter stripes 52 on the anode plate 40 are disclosed.

Abstract: A ferroelectric integrated circuit is provided in which a first layer of conducting lines (14) is formed over an insulating base layer (10). A first ferroelectric layer (16) is formed overlying the first layer of conducting lines (14). A second layer of conducting lines (18) is formed overlying the first ferroelectric layer (16) with each of the conducting lines of the second layer of conducting lines (18) being substantially perpendicular to the conducting lines of the first layer of conducting lines (14). Potentials placed on selected conducting lines in the first and second layers of conducting lines (14 and 18) polarize areas of the first ferroelectric layer (16) between intersections of the selected conducting lines. Multiple layers may be stacked to form a three-dimensional ferroelectric integrated circuit.

Abstract: A preferred embodiment of this invention comprises an oxidizable layer (e.g. tantalum 48), an oxygen gettering layer (e.g. platinum/tantalum mixture 34) overlaying the oxidizable layer, a noble metal layer (e.g. platinum 36) overlaying the oxygen gettering layer, and a high-dielectric-constant material layer (e.g. barium strontium titanate 38) overlaying the noble metal layer. The novel structures presented provide electrical connection to high-dielectric-constant materials without the disadvantages of current structures. The oxygen gettering layer controls oxygen diffusion, minimizing the formation of a resistive layer either in the lower electrode or at the lower electrode/substrate interface. The oxygen gettering layer acts as a gettering site for oxygen, where the oxygen oxidizes the reactive metal portion of the layer, leaving the noble metal portion of the layer intact. While the oxides/suboxides (e.g.

Abstract: A system and method for epitaxial growth of high purity materials on an atomic or molecular layer by layer basis wherein a substrate is placed in an evacuated chamber which is evacuated to a pressure of less than about 10.sup.-9 Torr and predetermined amounts of predetermined precursor gases are injected into the chamber from a location in the chamber closely adjacent the substrate to form the atomic or molecular layer at the surface of the substrate while maintaining the pressure at less than about 10.sup.-9 Torr in the chamber in regions thereof distant from the substrate. The precursor gases are provided from a plurality of tanks containing the precursor gases therein under predetermined pressure and predetermined ones of the tanks are opened to the chamber for predetermined time periods while maintaining the pressure in the tanks. A dose limiting structure is provided for directing predetermined amounts of the precursor gases principally at the substrate with a dose limiting directional structure.

Abstract: A method for forming single crystal aluminum films 14 on the surface of a substrate 12 (e.g. silicon {111} or Si{111}) is presented, comprising the steps of cleaning the substrate, then maintaining the substrate at certain temperature and pressure conditions while electrically neutral aluminum is deposited by a vacuum evaporation technique. Novel structures wherein single crystal aluminum contacts 20 fill via holes 18 in insulating layers 16 are presented. Novel structures wherein a single crystal aluminum film 14 exists on a substrate comprised of more than one crystalline material 12, 22 are presented.

Abstract: In one form of the invention, a method is disclosed for growing CaF.sub.2 on a silicon surface, comprising the steps of maintaining the silicon surface at a first temperature below approximately 500.degree. C., starting a deposition of CaF.sub.2 on the silicon surface, stopping the deposition, and then annealing the CaF.sub.2 in forming gas at a temperature below 600.degree. C.

Abstract: A process for testing leaks of a package (20) comprises the steps of introducing the package (20) into a chamber (30) and pressurizing the chamber (30) with a radioisotopic gas (14). After the package (20) has been removed from the chamber (30), a plurality of detectors (46) sense the gamma-ray emission from the individual packages (29). A conveyor system (44) can be employed to move the packages (20) during high volume production.

Abstract: The removal of residual impurities from semiconductor material is accomplished by solid state electromigration of the impurities from the semiconductor slice into a surrounding conductive liquid (e.g. Hg) which is maintained at a negative potential.