Abstract: A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A cooling device has a large number of closely spaced impinging jets, adjacent an impingement gap, with parallel return paths for supplying coolant flow for the impinging jets with the least possible pressure drop using an interdigitated, branched hierarchical manifold. Surface enhancement features spanning the impingement gap form U-shaped microchannels between single impinging jets and single outlets.

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: The invention relates to an integrated circuit stack (1) comprising a plurality of integrated circuit layers (2) and at least one cooling layer (3) arranged in a space between two circuit layers (2). The integrated circuit stack (1) is cooled using a cooling fluid (10) pumped through the cooling layer (3). The invention further relates to a method for optimizing a configuration of such an integrated circuit stack (1).

Abstract: A flexible, self-contained active multi-phase heat spreader apparatus for cooling electronic components, the heat spreader having fluid sealed between two plates and a pumping mechanism to actuate multi-phase flow of the fluid. Thermal energy from an electronic component in contact with the heat spreader is dissipated from a core region via the working fluid to the entire heat spreader, and then to a heat sink. Surface enhancement features located between the two plates aid transfer of thermal energy from a first metal plate into the fluid.

Abstract: The invention relates to an integrated circuit stack (1) comprising a plurality of integrated circuit layers (2) and at least one cooling layer (3) arranged in a space between two circuit layers (2). The integrated circuit stack (1) is cooled using a cooling fluid (10) pumped through the cooling layer (3). The invention further relates to a method for optimizing a configuration of such an integrated circuit stack (1).

Abstract: A method for transferring a pattern from an elastic stamp to a substrate in the presence of a third medium is described. A proximity contact is achieved between the stamp and the substrate. A layer of the third medium between the stamp and the substrate is controlled to a predetermined thickness. Stamps for carrying out this method are also described.

Abstract: A method for producing a plate with a first face with protrusions confined by first and second grooves includes steps of: etching recessed zones into a plate; depositing a photoresist layer on the plate; forming a passivation layer over the photoresist layer; removing the passivation layer at the bottom of the recessed zones; electroplating metal in the recessed zones; removing the passivation layer; removing the photoresist layer; and removing the semiconductor material to expose the first and second grooves.

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A method for transferring a pattern from an elastic stamp to a substrate in the presence of a third medium is described. A proximity contact is achieved between the stamp and the substrate. A layer of the third medium between the stamp and the substrate is controlled to a predetermined thickness. Stamps for carrying out this method are also described.

Abstract: A method for producing a monolayer of molecules on a surface comprises: loading a stamp with seed molecules; transferring seed molecules from the stamp to the surface; and, amplifying the seed molecules via an amplifying reaction to produce the monolayer. The method permit generation of complete monolayers from incomplete or sparse monolayers initially printed on the surface.

Abstract: A stamp for patterning onto a receiving surface of an object (101) according to a defined pattern (P) comprises a stamping surface (21) of a resilient diaphragm (20). The stamping surface is planar at rest. The pattern is reproduced on the stamping surface and the diaphragm is affixed to a rigid body (13) along a peripheral edge, so that a middle part of the diaphragm can move along a direction perpendicular to the stamping surface. The diaphragm (20) is more flexible near the peripheral edge than in the middle part. Then, the pattern (P) printed on a pseudo-spherical receiving surface (103) using the stamp exhibits few distortion.

Abstract: A stamp for transferring a pattern to a substrate in the presence of a third medium, includes a permeable hydrophilic matrix for guiding excess third medium away from the surface of the stamp.

Abstract: The present invention describes the synthesis of new fluorinated elastomers with very low glass transition temperatures (Tg), a good resistance to bases, gasoline and other carburants and good workability properties, these elastomers contain hexafluoropropene (HFP), perfluoro(4-methyl-3,6-dioxaoct-7-ene) sulfonyl fluoride (PFSO2F), vinylidene fluoride (VDF) and/or at least one fluorinated alkene and/or one vinyl perfluorinated ether. In a precise case, they are prepared by radical polymerisation of HFP and PFSO2F or by radical terpolymerisation HFP, PFSO2F and VDF in the presence of different organic initiator, such as peroxides, peresters or diazo compounds.

Abstract: A mechanism is provided for optimizing semiconductor packing in a three-dimensional (3D) very-large-scale integration (VLSI) device. The 3D VLSI device comprises a processor layer coupled, via a first set of coupling devices, to at least one signaling and input/output (I/O) layer. The 3D VLSI device further comprises a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the 3D VLSI device the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the three-dimensional VLSI device, and the at least one signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: An integrated circuitry structure includes at least first and second regions. An optical layer includes optical waveguides. A heat-conductive material transfers heat from at least the second region through the optical layer to a heat sink.

Abstract: An integrated circuit coupling device includes an integrated circuit package with N integrated circuit layers (L1-LN) arranged as a 3D stack; and a data transmission medium with n data transmission layers (l1-ln), wherein n?1 and N?2, and wherein the N integrated circuit layers are electrically connectable to the n data transmission layers.

Abstract: An integrated circuit coupling device includes an integrated circuit package; and an optical data transmission medium connected to the integrated circuit package, and comprising a movable coolant, adapted to remove heat from the integrated circuit package, in operation.

Abstract: A mechanism is provided for a thermal power plane that delivers power and constitutes minimal thermal resistance. The mechanism comprises a processor layer coupled, via a first set of coupling devices, to a signaling and input/output (I/O) layer and a power delivery layer coupled, via a second set of coupling devices, to the processor layer. In the mechanism, the power delivery layer is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism. In the mechanism, the power delivery layer comprises a plurality of conductors, a plurality of insulating materials, one or more ground planes, and a plurality of through laminate vias. In the mechanism, the signaling and input/output (I/O) layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.

Abstract: A mechanism is provided for integrated power delivery and distribution via a heat sink. The mechanism comprises a processor layer coupled to a signaling and input/output (I/O) layer via a first set of coupling devices and a heat sink coupled to the processor layer via a second set of coupling devices. In the mechanism, the heat sink comprises a plurality of grooves on one face, where each groove provides either a path for power or a path for ground to be delivered to the processor layer. In the mechanism, the heat sink is dedicated to only delivering power and does not provide data communication signals to the elements of the mechanism and the signaling and I/O layer is dedicated to only transmitting the data communication signals to and receiving the data communications signals from the processor layer and does not provide power to the elements of the processor layer.