Abstract: A semiconductor device includes a memory cell array and a plurality of read and write circuits. The memory cell array includes a plurality of planes. Any one of the read and write circuits generates parity data based on data sequentially received from a controller through a channel.

Abstract: A storage device includes a nonvolatile memory device including a memory cell array, a page buffer, and a map buffer and a memory controller. The memory cell array is configured to store a plurality of map entries each indicating a mapping relationship between a logical address and a physical address each. A page buffer is configured to store the plurality of map entries stored in the nonvolatile memory device having a map buffer index. The memory controller is configured to provide a first map read command and a second map read command to the nonvolatile memory device to convert a logical address from a host into a physical address and perform operation.

Abstract: A leakage detection circuit may include: a comparison circuit configured to compare an input voltage, which changes based on the level of an operation voltage node, to a reference voltage and configured to output a detection signal; and a state decision circuit configured to determine a count value that corresponds to a determination period based on the detection signal and configured to output leakage state information based on the count value.

Abstract: A semiconductor memory device includes a plurality of memory blocks, a peripheral circuit, control logic, and a status checker. Each of the plurality of memory blocks includes a plurality of physical pages. The peripheral circuit is configured to perform a program operation, an erase operation, or a read operation on a selected memory block among the plurality of memory blocks. The control logic controls the program operation, the erase operation, or the read operation of the peripheral circuit. The status checker checks a ratio of a programmed page among the physical pages included in the plurality of memory blocks.

Abstract: A storage device includes a memory device including a plurality of memory blocks including a plurality of memory cells respectively connected to a plurality of word lines which are vertically stacked, and a memory controller configured to control the memory device to determine an attribute of a plurality of write data corresponding to a write request in response to the write request provided from a host, set a program voltage used for a program operation of storing write data having the same attribute of the write data among the plurality of write data in the same memory block based on a lookup table including the attribute of the write data and program information on the program voltage according to positions of the plurality of word lines, and perform the program operation according to the set program voltage.

Abstract: A leakage detection circuit may include: a comparison circuit configured to compare an input voltage, which changes based on the level of an operation voltage node, to a reference voltage and configured to output a detection signal; and a state decision circuit configured to determine a count value that corresponds to a determination period based on the detection signal and configured to output leakage state information based on the count value.

Abstract: The present technology relates to an electronic device. A memory device having improved memory block management performance according to the present technology includes a memory block, a peripheral circuit, and a control logic. The peripheral circuit performs a read operation and a program operation on a selected physical page among a plurality of physical pages. The control logic controls the peripheral circuit to read first logical page data stored in a first physical page and second logical page data stored in a second physical page among the plurality of physical pages, and additionally program the second logical page data into the first physical page using the read first and second logical page data.

Abstract: A memory device includes a plurality of memory blocks, a read count storage, and a read reclaim processor. The read count storage stores read count information including a read count of each of the plurality of memory blocks. The read reclaim processor provides a memory controller with a status read response including a status code representing a priority order of a read reclaim operation on a target block, in response to a status read command received from the memory controller.

Abstract: A storage device for performing a garbage collection operation using a partial block erase operation includes: a memory device including a plurality of main blocks each including a plurality of sub-blocks; and a memory controller configured to perform a garbage collection operation for securing free blocks in which no data is stored, among the main blocks, wherein the memory controller includes a write handler configured to erase at least a portion of a target block, among the main blocks, according to whether an amount of valid data in at least one victim block exceeds a storage capacity of one main block.

Abstract: Provided herein may be a storage device and a method of operating the same. The storage device may include: a memory device including a memory cell array and a page buffer; and a memory controller including a write buffer. The memory device may further include a page buffer state determiner configured to generate a page buffer state signal based on a state of the page buffer and provide the page buffer state signal to the memory controller. The memory controller may further include a write operation controller configured to provide data provided from a host to either the page buffer or the write buffer in response to the page buffer state signal, and control the memory device to program data stored in the page buffer to the memory cell array based on the state of the write buffer.

Abstract: The present disclosure relates to a storage device and a method of operating the same. The storage device includes a memory device including a memory cell array that stores normal data and map data, and a memory controller configured to control overall operation, including program operation, read operation, and erase operation, of the memory device in response to requests from a host. The memory device is configured to, during a map data load operation, transmit first map data to the memory controller by reading the first map data among the map data stored in the memory cell array, and transmit second map data to a page buffer group of the memory device by reading the second map data among the map data.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory device having reduced latency includes a plurality of memory cells, an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value, which is the number of memory cells read as a first memory cell based on data read from the plurality of memory cells among the plurality of memory cells, and a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on the data read from the plurality of memory cells using the default read voltage, in response to an optimum read voltage setting command input from a memory controller, and generate a first optimum read voltage based on the cell count value corresponding to the default read voltage and the optimum read voltage information.

Abstract: A storage device according to an embodiment includes a nonvolatile memory device including a memory cell array configured to store a plurality of map entries each indicating a mapping relationship between a logical address and a physical address, and a page buffer configured to store the plurality of map entries, a volatile memory device configured to be loaded with map entries, from the plurality of map entries, stored in the nonvolatile memory device, and a memory controller configured to control the nonvolatile memory device to convert a logical address provided from a host into a physical address and perform an operation corresponding to a request on the physical address, in response to the request provided from the host.

Abstract: Provided herein may be a memory system and a method of operating the same. The memory system may include a memory device configured to include a plurality of memory blocks and copy data from victim blocks among the plurality of memory blocks into a target memory block during a garbage collection operation, and a memory controller configured to control the memory device to perform the garbage collection operation, and configured to control the memory device, during the garbage collection operation, to erase the data stored in the victim blocks using a multi-erase method.

Abstract: A storage device according to an embodiment includes a memory device including a plurality of memory blocks including a plurality of memory cells respectively connected to a plurality of word lines which are vertically stacked, and a memory controller configured to control the memory device to determine an attribute of a plurality of write data corresponding to a write request in response to the write request provided from a host, set a program voltage used for a program operation of storing write data having the same attribute of the write data among the plurality of write data in the same memory block based on a lookup table including the attribute of the write data and program information on the program voltage according to positions of the plurality of word lines, and perform the program operation according to the set program voltage.

Abstract: A memory system includes a status information register configured for checking threshold voltages of select transistors included in memory blocks, storing status information on a check result, and outputting a code based on the status information, a status monitor configured to receive the code from the status information register, determine a number of select transistors that have shifted according to the code, and output status signal based on the number of the select transistors that have shifted, and a central processing unit configured for outputting a setup command set for setting parameters of the memory blocks, outputting a re-program command set for re-programming the select transistors, or outputting a bad block address for processing the memory blocks as bad blocks in response to the status signals.

Abstract: The present technology relates to an electronic device. According to the present technology, a memory device having reduced latency includes a plurality of memory cells, an optimum read voltage information storage configured to store optimum read voltage information determined according to a cell count value, which is the number of memory cells read as a first memory cell based on data read from the plurality of memory cells among the plurality of memory cells, and a read voltage controller configured to calculate a cell count value corresponding to a default read voltage based on the data read from the plurality of memory cells using the default read voltage, in response to an optimum read voltage setting command input from a memory controller, and generate a first optimum read voltage based on the cell count value corresponding to the default read voltage and the optimum read voltage information.

Abstract: There are provided a microcontroller, a memory system having the same, and a method for operating the same. A memory system includes: a semiconductor memory performing a scanning operation on ROM data stored in a microcontroller in a test operation and outputting a result of the scanning operation as a status output signal; and a controller for determining whether an error exists in the ROM data, using the status output signal.

Abstract: The present disclosure relates to a storage device and a method of operating the same. The storage device includes a memory device including a memory cell array that stores normal data and map data, and includes a memory controller configured to control overall operation, including program operation, read operation, and erase operation, of the memory device in response to requests from a host. The memory device is configured to, during a map data load operation, transmit first map data to the memory controller by reading the first map data among the map data stored in the memory cell array, and transmit second map data to a page buffer group of the memory device by reading the second map data among the map data.

Abstract: A memory system includes a plurality of memory devices configuring a plurality of ways, and a memory controller communicating with the plurality of memory devices through a channel, wherein each of the plurality of memory devices includes a device queue, and wherein the device queue queues a plurality of controller commands inputted from the memory controller.