Abstract: A noise protector includes a first noise control block for NORing an input signal and a first trimmed input signal and providing an output; a second noise control block for NANDing the input signal and a second trimmed input signal and providing an output; and an output signal generation block for outputting an output signal removed of noise in response to the outputs of the first noise control block and the second noise control block.

Abstract: A multi-plane type flash memory device comprises a plurality of planes each including a plurality of memory cell blocks, page buffers each latching an input data bit to be output to its corresponding plane or latching an output data bit to be received from the corresponding plane, cache buffers each storing an input or output data bits in response to one of cache input control signals and each transferring the stored data bit to the page buffer or an external device in response to one of cache output control signals, and a control logic circuit generating the cache input and output control signals in response to command and chip enable signals containing plural bits. The program and read operations for the plural planes are conducted simultaneously in response to the chip enable signal containing the plural bits, which increases an operation speed and data throughput processed therein.

Abstract: A noise protector includes a first noise control block for NORing an input signal and a first trimmed input signal and providing an output; a second noise control block for NANDing the input signal and a second trimmed input signal and providing an output; and an output signal generation block for outputting an output signal removed of noise in response to the outputs of the first noise control block and the second noise control block.

Abstract: A flash memory device with a reduced access time. The flash memory device executes an error detection and correction operation while encoding or decoding transmission and reception signals with a host apparatus. The flash memory device utilizes a simplified design algorithm and reduces an access time.

Abstract: A flash memory device with a reduced access time. The flash memory device executes an error detection and correction operation while encoding or decoding transmission and reception signals with a host apparatus. The flash memory device utilizes a simplified design algorithm and reduces an access time.