Abstract: Semiconductor circuits are provided for emulating neuron firing process using a positive feedback transistor having first and second gate electrodes in the longitudinal direction of a channel region. The first gate electrode is connected to a gate electrode of a first p-channel MOSFET to be an input terminal and the second gate electrode is connected to a drain to be applied with a supply voltage. Thus electrons and holes can accumulate separately in a channel region (i.e., a body) under each of the gate electrodes by applying input signals to the input terminal and drastically reduce the wasted power consumption in the non-fired neurons because the current is turned on and off only at a moment that corresponds to a firing of the neuron. Thus, the semiconductor circuits can be driven by low power and have the same level of endurance as a general MOSFET.

Abstract: An integrated circuit emulating a neural system and a fabricating method thereof are provided. A synapse device array that imitates a brain neural system (i.e., a central nervous system) requiring high integration on the same substrate is formed by stacking one or more layers on a lower portion, and a neuron circuit of a peripheral nervous system having sensory and motor neurons connected to the brain neural system is formed on an upper portion.

Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectio

Abstract: A resistive random access memory device having a nano-scale tip and a nanowire is provided. A memory array using the same also is provided and fabrication method thereof. A technique is provided for forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate and a top electrode being formed of a nanowire and a technique forming a resistive random access memory device at a location intersected with each other in order that an area of each memory cell is minimized and that an electric field is focused on the tip of the bottom electrode across the top electrode.

Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectio

Abstract: A resistive random access memory device having a nano-scale tip and a nanowire is provided. A memory array using the same also is provided and fabrication method thereof. A technique is provided for forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate and a top electrode being formed of a nanowire and a technique forming a resistive random access memory device at a location intersected with each other in order that an area of each memory cell is minimized and that an electric field is focused on the tip of the bottom electrode across the top electrode.

Abstract: A semiconductor device includes a structure on a substrate and a plurality of gate-all-around devices on the structure. The structure includes a plurality of sacrificial layers and a plurality of active layers alternately stacked on one another. The sacrificial layers have different widths and the active layers have different widths to form multiple stepped layers on the substrate. The gate-all-around devices are on respective ones the multiple stepped layers.

Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectio

Abstract: The present invention provides a semiconductor circuit for emulating neuron firing process having a floating body device instead of the conventional capacitor. By using a floating body to store excess holes generated by impact ionization, it is possible to emulate signal accumulation of a neuron, trigger firing when the storage is in excess of a predetermined threshold value, and return to an original state after the firing.

Abstract: A resistive random access memory device is provided with a tunneling insulator layer between a resistance change layer and a bottom electrode. Thus, it is possible: to raise the selection (on/off) ratio by the current of a direct tunneling induced by low voltage in the unselected cell and the current of an F-N tunneling induced by high voltage in the selected cell, to efficiently suppress the leakage current in the read operation, to make a low current operation less ?A level by controlling the thickness of the tunneling insulator layer, and to be simultaneously fabricated together with circuit devices by forming the bottom electrodes (word lines) with a semiconductor material.

Abstract: The present invention relates to a resistive random access memory device having a nano-scale tip, memory array using the same and fabrication method thereof. Especially, the present invention provides a technique forming a bottom electrode having an upwardly protruding tapered tip structure through etching a semiconductor substrate in order that an electric field is focused on the tip of the bottom electrode across a top electrode and that a region where conductive filaments are formed is maximally minimized or localized.

Abstract: A method of controlling a 3D non-volatile memory device includes initially leveling threshold voltages of the string selection transistors disposed in one or more of the plurality of memory layers to have a predetermined target level; applying a first time varying erase voltage signal having a first time varying section to a first plurality of channel lines of a first memory layer selected among the plurality of memory layers comprising the initially leveled string selection transistors; and setting threshold voltages of the initially leveled string selection transistors in the first memory layer by controlling each of the plurality of string selection lines respectively coupled with the initially leveled string selection transistors during the first time varying section of the first time varying erase voltage signal.

Abstract: A 3D non-volatile memory device may include a dummy string selection line, string selection lines, wordlines, bitlines, a ground selection line, and memory layers. Each of the memory layers comprising channel lines respectively coupled to the bitlines via first ends and coupled to a common source line of the memory layer via second ends. The dummy string selection line, the string selection lines, the wordlines, and the ground selection line intersect with the channel lines, and each of the channel lines defines a memory string. Initializing the 3D non-volatile memory device may include programming string selection transistors coupled with the string selection lines to have one or more threshold values, and programming a dummy string selection transistor coupled with the dummy string selection line to have a predetermined threshold value, such that the dummy string selection transistor together with the string selection transistors function as string selection transistors.

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract: A 3D non-volatile memory device may include a dummy string selection line, string selection lines, wordlines, bitlines, a ground selection line, and memory layers. Each of the memory layers comprising channel lines respectively coupled to the bitlines via first ends and coupled to a common source line of the memory layer via second ends. The dummy string selection line, the string selection lines, the wordlines, and the ground selection line intersect with the channel lines, and each of the channel lines defines a memory string. Initializing the 3D non-volatile memory device may include programming string selection transistors coupled with the string selection lines to have one or more threshold values, and programming a dummy string selection transistor coupled with the dummy string selection line to have a predetermined threshold value, such that the dummy string selection transistor together with the string selection transistors function as string selection transistors.

Abstract: A method of initializing and programming a 3D non-volatile memory device includes applying a first program voltage to a selected string selection line coupled to a selected memory layer among the plurality of memory layers; verifying whether threshold voltages of a plurality of string selection transistors reach a target value to determine the plurality of string selection transistors as programmed string selection transistors or unprogrammed string selection transistors; programming memory cell transistors of one or more of memory strings coupled with the programmed string selection transistors to have a predetermined threshold voltage, by applying a second program voltage to a selected wordline among the plurality of wordlines; and program-inhibiting channel lines of the programmed string selection transistors using the programmed memory cell transistors as screening transistors and applying a third program voltage to the selected string selection line to selectively program the unprogrammed string selectio

Abstract: A method of controlling a 3D non-volatile memory device includes initially leveling threshold voltages of the string selection transistors disposed in one or more of the plurality of memory layers to have a predetermined target level; applying a first time varying erase voltage signal having a first time varying section to a first plurality of channel lines of a first memory layer selected among the plurality of memory layers comprising the initially leveled string selection transistors; and setting threshold voltages of the initially leveled string selection transistors in the first memory layer by controlling each of the plurality of string selection lines respectively coupled with the initially leveled string selection transistors during the first time varying section of the first time varying erase voltage signal.

Abstract: A method for fabricating a semiconductor device includes forming a first mask on a substrate, forming a first side wall of a fin by performing a first etching of the substrate using the first mask, forming a second mask on the substrate, the second mask being different from the first mask, and forming a second side wall of the fin by performing a second etching of the substrate using the second mask.

Abstract: A semiconductor device has gate-all-around devices formed in respective regions on a substrate. The gate-all-around devices have nanowires at different levels. The threshold voltage of a gate-all-around device in first region is based on a thickness of an active layer in an adjacent second region. The active layer in the second region may be at substantially a same level as the nanowire in the first region. Thus, the nanowire in the first region may have a thickness based on the thickness of the active layer in the second region, or the thicknesses may be different. When more than one active layer is included, nanowires in different ones of the regions may be disposed at different heights and/or may have different thicknesses.

Abstract: A resistive random access memory device is provided with a tunneling insulator layer between a resistance change layer and a bottom electrode. Thus, it is possible: to raise the selection (on/off) ratio by the current of a direct tunneling induced by low voltage in the unselected cell and the current of an F-N tunneling induced by high voltage in the selected cell, to efficiently suppress the leakage current in the read operation, to make a low current operation less ?A level by controlling the thickness of the tunneling insulator layer, and to be simultaneously fabricated together with circuit devices by forming the bottom electrodes (word lines) with a semiconductor material.