Patents by Inventor Byung Joon AN

Byung Joon AN has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10108758
    Abstract: Described herein is a method and system that provides access to numerous connected devices in a device bank and allows remote interaction and control of aspects of the connected devices using a remote management system. In an embodiment, the method comprises the configuring of one or more connected devices in the device bank to mimic an end user's connected device configuration and environment in order to resolve an issue with the end user's connected device. In other embodiments, the connected devices in the device bank can be used by end users such as developers to test and diagnose new applications and by remote support technicians to train themselves on connected devices.
    Type: Grant
    Filed: November 8, 2013
    Date of Patent: October 23, 2018
    Assignee: AetherPal Inc.
    Inventors: Deepak Gonsalves, Pooja Chengappa, Ramesh Parmar, Subramanyam Ayyalasomayajula, Mahadevan Viswanathan, Byung Joon Oh
  • Publication number: 20180300182
    Abstract: A hypervisor-based virtual machine isolation apparatus and method. The hypervisor-based virtual machine isolation method performed by the hypervisor-based virtual machine isolation apparatus includes when a hypervisor starts to run virtual machines, allocating one or more colors to each of the virtual machines, allocating a page frame corresponding to the allocated colors to the corresponding virtual machine, allocating an accessible core depending on the colors of the virtual machine, and performing isolation between virtual machines corresponding to an identical color by changing a temporal/spatial scheduling order between the virtual machines corresponding to the identical color.
    Type: Application
    Filed: November 13, 2017
    Publication date: October 18, 2018
    Inventors: Woomin HWANG, Sung-Jin KIM, Byung-Joon KIM, Hyunyi YI, Chulwoo LEE, Hyoung-Chun KIM
  • Patent number: 10101366
    Abstract: A protective relaying system and a data collection method thereof capable of enhancing a data collection efficiency and effectiveness is provided. The protective relaying system may include a plurality of protective relaying modules respectively connected to a switch to control the operation of the switch; a server module coupled to one of the plurality of protective relaying modules, and connected to the plurality of protective relaying modules, respectively, to sequentially collect and store data of the plurality of protective relaying modules; and a remote monitoring unit connected to the server module to collectively receive and collect the stored data of the plurality of protective relaying modules from the server module.
    Type: Grant
    Filed: June 8, 2015
    Date of Patent: October 16, 2018
    Assignee: LSIS CO., LTD.
    Inventor: Byung Joon Jeon
  • Publication number: 20180294235
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Publication number: 20180294236
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Publication number: 20180246710
    Abstract: A software update apparatus and method in a virtualized environment. The software update method performed by a software update apparatus in a virtualized environment includes monitoring an operation that is invoked when software is updated in a guest operating system area, creating a software profile by analyzing results of the monitoring, mounting a virtual disk image for a target virtual machine in a target directory in a virtual machine monitor area, and incorporating update information of at least one of a file and a registry that are specified in the software profile into the target directory in which the virtual disk image is mounted.
    Type: Application
    Filed: July 21, 2017
    Publication date: August 30, 2018
    Inventors: Sung-Jin KIM, Woomin HWANG, Byung-Joon KIM, Hyun-Yi YI, Chul-Woo LEE, Hyoung-Chun KIM
  • Patent number: 10058952
    Abstract: A bonding stage is provided. The bonding stage includes a first heater disposed under a first region of a substrate having a plurality of semiconductor chips disposed thereon, a second heater disposed under a second region different from the first region of the substrate, a cooler disposed under the first heater and the second heater and blocking heat of the first heater and heat of the second heater from being transferred to lower portions of the first heater and the second heater, and a thin plate disposed on the first heater and the second heater to support the substrate and transferring the heat of the first heater and the heat of the second heater to the substrate, wherein the first heater and the second heater are independently operated.
    Type: Grant
    Filed: November 1, 2016
    Date of Patent: August 28, 2018
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Seung-Dae Seok, Sang Yoon Kim, Hui Jae Kim, Jae Bong Shin, Byung Joon Lee
  • Patent number: 10002401
    Abstract: A method of processing a graphics command may include: receiving the graphics command from an apparatus that executes an application; selecting at least one shader included in the graphics command to be processed by a graphics processor; creating a shader program using the selected at least one shader; searching for a shader program corresponding to the created shader program from among one or more previously compiled shader programs; and outputting a found shader program.
    Type: Grant
    Filed: June 30, 2016
    Date of Patent: June 19, 2018
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Kyung-su Kim, Byung-joon Chang, Bong-hoon Park, Chan-min Park, Woo-ram Ann, Tae-young Lee, Joo-young Jung, Cheul-hee Hahm
  • Patent number: 9997468
    Abstract: An integrated circuit packaging system and method of manufacture thereof includes: a substrate with internal circuitry between a substrate top side, a substrate bottom side, and vertical sides; an integrated circuit coupled to the internal circuitry; a molded package body formed directly on the integrated circuit and the substrate top side of the substrate; and a conductive conformal shield structure applied directly on the molded package body, the vertical sides, and to extend below the substrate bottom side coupled to the internal circuitry.
    Type: Grant
    Filed: April 5, 2016
    Date of Patent: June 12, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, KyoungHee Park, Yaojian Lin, KyoWang Koo, In Sang Yoon, SeungYong Chai, SungWon Cho, SungSoo Kim, Hun Teak Lee, DeokKyung Yang
  • Patent number: 9997048
    Abstract: Embodiments of a power failure monitoring device of a digital protection relay capable of preventing a relay operation error and a data loss by determining a power failure when an electric power voltage being detected is dropped to be equal to or less than a prestored power failure reference voltage to enable a controller to perform a power failure preparation operation are provided.
    Type: Grant
    Filed: July 20, 2016
    Date of Patent: June 12, 2018
    Assignee: LSIS CO., LTD.
    Inventor: Byung-Joon Jeon
  • Patent number: 9986183
    Abstract: A lens distortion correction device and an application processor having the same include a distortion correction unit configured to correct a distorted image into an undistorted image and an image enhancement unit configured to improve the undistorted image using a high-frequency component of the distorted image.
    Type: Grant
    Filed: January 13, 2017
    Date of Patent: May 29, 2018
    Assignees: Samsung Electronics Co., Ltd., Chung-Ang University Industry—Academy Cooperation Foundation
    Inventors: Byung-Joon Baek, Joon-Ki Paik, Tae-Chan Kim, Dong-Gyun Kim, Jin-Ho Park
  • Patent number: 9954775
    Abstract: A software-defined network (SDN) system and method for implementing the same can construct a network having flexible network topology by abstracting switches and controllers, as well as a host connected to said switches, and controllers, thereby increasing scalability of a hierarchical SDN network. The SDN system includes a host part, an SDN switch part, and an SDN controller part.
    Type: Grant
    Filed: November 25, 2015
    Date of Patent: April 24, 2018
    Assignee: ELECTRONICS AND TELECOMMUNICATIONS RESEARCH INSTITUTE
    Inventors: Sae Hyong Park, Byung Joon Lee, Ji Soo Shin, Tae Hong Kim, Jae Ho You
  • Patent number: 9934998
    Abstract: A semiconductor device comprises a carrier including an adhesive disposed over the carrier. The semiconductor device further comprises a semiconductor wafer including a plurality of semiconductor die separated by a non-active region. A plurality of bumps is formed over the semiconductor die. The semiconductor wafer is mounted to the carrier with the adhesive disposed around the plurality of bumps. Irradiated energy is applied to the non-active region to form a modified region within the non-active region. The semiconductor wafer is singulated along the modified region to separate the semiconductor die. The semiconductor wafer is singulated along the modified region by applying stress to the semiconductor wafer. The adhesive is removed from around the plurality of bumps after singulating the semiconductor wafer. The semiconductor wafer includes a plurality of semiconductor die comprising through silicon vias. The modified region optionally includes a plurality of vertically stacked modified regions.
    Type: Grant
    Filed: December 14, 2016
    Date of Patent: April 3, 2018
    Assignee: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Won Kyoung Choi
  • Patent number: 9873148
    Abstract: A frame for a self-piercing rivet system that can provide bearing capacity for joining a rivet to a plate by using an anvil die and a punch unit is disclosed.
    Type: Grant
    Filed: December 30, 2014
    Date of Patent: January 23, 2018
    Assignee: SUNGWOO HITECH CO., LTD.
    Inventors: Byung Joon Park, Mun Yong Lee, Tae Young Kang, Do Hyung Kim, Sung Ho Lee
  • Publication number: 20180010012
    Abstract: This invention relates to a resin composition for a hard coating, including a siloxane resin configured such that compounds including an alkoxysilane and an alkoxy metal compound are chemically bound, and to a hard coating film including a hard coating layer formed using the resin composition.
    Type: Application
    Filed: December 31, 2015
    Publication date: January 11, 2018
    Applicant: KOLON INDUSTRIES, INC.
    Inventors: Sang Hyun AHN, Hak Yong WOO, Hak Gee JUNG, Dong Hee LEE, Byung Joon AN, Hang Geun KIM
  • Publication number: 20170358615
    Abstract: Provided are an image sensor and an imaging apparatus. The image sensor of a multi-layered sensor structure, the image sensor includes a plurality of sensing pixels, each of the plurality of sensing pixels including a micro lens configured to collect light, a first photoelectric converter configured to convert light of a first wavelength band into an electric signal, and a second photoelectric converter formed on a substrate configured to convert incident light into the electric signal, wherein a central axis of the second photoelectric converter is spaced apart from an optical axis of the micro lens.
    Type: Application
    Filed: August 7, 2017
    Publication date: December 14, 2017
    Applicant: Samsung Electronics Co., Ltd.
    Inventor: Byung-joon Baek
  • Publication number: 20170330840
    Abstract: A semiconductor device has a first component. A modular interconnect structure is disposed adjacent to the first component. A first interconnect structure is formed over the first component and modular interconnect structure. A shielding layer is formed over the first component, modular interconnect structure, and first interconnect structure. The shielding layer provides protection for the enclosed semiconductor devices against EMI, RFI, or other inter-device interference, whether generated internally or from external semiconductor devices. The shielding layer is electrically connected to an external low-impedance ground point. A second component is disposed adjacent to the first component. The second component includes a passive device. An LC circuit includes the first component and second component. A semiconductor die is disposed adjacent to the first component. A conductive adhesive is disposed over the modular interconnect structure.
    Type: Application
    Filed: July 31, 2017
    Publication date: November 16, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Byung Joon Han, Rajendra D. Pendse, Il Kwon Shim, Pandi C. Marimuthu, Won Kyoung Choi, Linda Pei Ee Chua
  • Publication number: 20170330367
    Abstract: An image processing apparatus and an image processing method are provided. The image processing method in the image processing apparatus according to the present invention includes: sequentially storing, in a memory, a non-shadow ray and at least one shadow ray derived from the non-shadow ray; and performing a shading operation using the sequentially stored non-shadow ray and at least one shadow ray.
    Type: Application
    Filed: September 9, 2015
    Publication date: November 16, 2017
    Inventors: Byung-joon CHANG, Kyung-su KIM, Won-jun ROH, Jae-woong LEE, Chan-min PARK, Gun-ill LEE, In-sang CHO
  • Publication number: 20170294406
    Abstract: A semiconductor device includes a standardized carrier. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. The semiconductor wafer is singulated through a first portion of the base semiconductor material to separate the semiconductor die. The semiconductor die are disposed over the standardized carrier. A size of the standardized carrier is independent from a size of the semiconductor die. An encapsulant is deposited over the standardized carrier and around the semiconductor die. An interconnect structure is formed over the semiconductor die while leaving the encapsulant devoid of the interconnect structure. The semiconductor device is singulated through the encapsulant. Encapsulant remains disposed on a side of the semiconductor die.
    Type: Application
    Filed: June 19, 2017
    Publication date: October 12, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Byung Joon Han, Il Kwon Shim, Yaojian Lin, Pandi C. Marimuthu
  • Publication number: 20170271305
    Abstract: A semiconductor device includes a semiconductor die and an encapsulant deposited over and around the semiconductor die. A semiconductor wafer includes a plurality of semiconductor die and a base semiconductor material. A groove is formed in the base semiconductor material. The semiconductor wafer is singulated through the groove to separate the semiconductor die. The semiconductor die are disposed over a carrier with a distance of 500 micrometers (?m) or less between semiconductor die. The encapsulant covers a sidewall of the semiconductor die. A fan-in interconnect structure is formed over the semiconductor die while the encapsulant remains devoid of the fan-in interconnect structure. A portion of the encapsulant is removed from a non-active surface of the semiconductor die. The device is singulated through the encapsulant while leaving encapsulant disposed covering a sidewall of the semiconductor die. The encapsulant covering the sidewall includes a thickness of 50 ?m or less.
    Type: Application
    Filed: June 6, 2017
    Publication date: September 21, 2017
    Applicant: STATS ChipPAC Pte. Ltd.
    Inventors: Yaojian Lin, Pandi C. Marimuthu, Il Kwon Shim, Byung Joon Han