Abstract: A memory device prevents generation of an abnormal column address. The memory device includes: a memory cell array; and a column address controller configured to generate a column address of the memory cell array in response to a column address control signal, wherein the column address controller enables the column address control signal when an address signal is input, and wherein the address signal includes a column address signal corresponding to the column address.

Abstract: A semiconductor memory device includes a memory cell array, a read/write circuit, and a control logic. The memory cell array includes a plurality of memory blocks. The read/write circuit performs a read/write operation on a selected page of the memory cell array. The address decoder stores bad block marking data on each of the plurality of memory blocks, and outputs the bad block marking data in response to an address signal. The control logic controls the read/write circuit to test whether a defect has occurred in the plurality of memory blocks, and controls the address decoder to store, as the bad block marking data, a test result representing whether the defect has occurred in the plurality of memory blocks.

Abstract: A semiconductor memory device includes a memory cell array, a read/write circuit, and a control logic. The memory cell array includes a plurality of memory blocks. The read/write circuit performs a read/write operation on a selected page of the memory cell array. The address decoder stores bad block marking data on each of the plurality of memory blocks, and outputs the bad block marking data in response to an address signal. The control logic controls the read/write circuit to test whether a defect has occurred in the plurality of memory blocks, and controls the address decoder to store, as the bad block marking data, a test result representing whether the defect has occurred in the plurality of memory blocks.

Abstract: The invention relates to a memory device and a memory system having the same. The memory device includes a memory block including a plurality of pages, a peripheral circuit including a plurality of buffers sensing data stored in a selected page of the plurality of pages, temporarily storing high usage frequency data, and outputting the data, and a control circuit controlling the peripheral circuit to output the data after performing a sensing operation on the selected page, storing the high usage frequency data to at least one of the buffers, or outputting the high usage frequency data without performing the sensing operation in response to a read command.

Abstract: Provided herein is a fail bit counter. The fail bit counter includes a pass/fail data receiver receiving pass/fail data indicating whether memory cells coupled to a bit line sequentially pass or fail, and a fail bit accumulator receiving a fail bit generation signal from the pass/fail data receiver, and accumulating and counting fail bits which are generated.

Abstract: A memory device prevents generation of an abnormal column address. The memory device includes: a memory cell array; and a column address controller configured to generate a column address of the memory cell array in response to a column address control signal, wherein the column address controller enables the column address control signal when an address signal is input, and wherein the address signal includes a column address signal corresponding to the column address.

Abstract: Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory cell array including a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation, which includes a plurality of program loops, on selected memory cells among the plurality of memory cells and a control circuit configured to control the peripheral circuit so that a program voltage applied to a selected word line, to which the selected memory cells are coupled, is stepwisely increased from a program start voltage to a target program voltage by a step voltage, which is a voltage increment of the program voltage, during a preset time period of a respective program loop.

Abstract: Provided herein is a fail bit counter. The fail bit counter includes a pass/fail data receiver receiving pass/fail data indicating whether memory cells coupled to a bit line sequentially pass or fail, and a fail bit accumulator receiving a fail bit generation signal from the pass/fail data receiver, and accumulating and counting fail bits which are generated.

Abstract: Provided herein are a semiconductor memory device and a method of operating the semiconductor memory device. The semiconductor memory device includes a memory cell array including a memory cell array including a plurality of memory cells, a peripheral circuit configured to perform a program operation, which includes a plurality of program loops, on selected memory cells among the plurality of memory cells and a control circuit configured to control the peripheral circuit so that a program voltage applied to a selected word line, to which the selected memory cells are coupled, is stepwisely increased from a program start voltage to a target program voltage by a step voltage, which is a voltage increment of the program voltage, during a preset time period of a respective program loop.

Abstract: The invention relates to a memory device and a memory system having the same. The memory device includes a memory block including a plurality of pages, a peripheral circuit including a plurality of buffers sensing data stored in a selected page of the plurality of pages, temporarily storing high usage frequency data, and outputting the data, and a control circuit controlling the peripheral circuit to output the data after performing a sensing operation on the selected page, storing the high usage frequency data to at least one of the buffers, or outputting the high usage frequency data without performing the sensing operation in response to a read command.

Abstract: A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for activating/deactivating a first signal based on the counting information, first rising information, and first falling information; a second signal generation unit suitable for activating/deactivating a second signal based on the counting information, second rising information, second falling information, and the first falling information; and a control signal driving unit suitable for driving a control signal in response to the first and second signals.

Abstract: A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for activating/deactivating a first signal based on the counting information, first rising information, and first falling information; a second signal generation unit suitable for activating/deactivating a second signal based on the counting information, second rising information, second falling information, and the first falling information; and a control signal driving unit suitable for driving a control signal in response to the first and second signals.

Abstract: A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for activating/deactivating a first signal based on the counting information, first rising information, and first falling information; a second signal generation unit suitable for activating/deactivating a second signal based on the counting information, second rising information, second falling information, and the first falling information; and a control signal driving unit suitable for driving a control signal in response to the first and second signals.

Abstract: A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for activating/deactivating a first signal based on the counting information, first rising information, and first falling information; a second signal generation unit suitable for activating/deactivating a second signal based on the counting information, second rising information, second falling information, and the first falling information; and a control signal driving unit suitable for driving a control signal in response to the first and second signals.

Abstract: There are provided a storage device, a memory system having the same, and an operating method thereof. A storage device includes a plurality of memory blocks for storing data, a peripheral circuit for selecting multiple memory blocks from among the plurality of memory blocks and simultaneously performing an erase operation on the multiple memory blocks, and a control circuit for controlling the peripheral circuit so that the multiple memory blocks are simultaneously erased, and an erase operation and an erase verification operation of a selected memory block from among the multiple memory blocks are performed.

Abstract: There are provided a storage device, a memory system having the same, and an operating method thereof. A storage device includes a plurality of memory blocks for storing data, a peripheral circuit for selecting multiple memory blocks from among the plurality of memory blocks and simultaneously performing an erase operation on the multiple memory blocks, and a control circuit for controlling the peripheral circuit so that the multiple memory blocks are simultaneously erased, and an erase operation and an erase verification operation of a selected memory block from among the multiple memory bocks are performed.

Abstract: A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for activating/deactivating a first signal based on the counting information, first rising information, and first falling information; a second signal generation unit suitable for activating/deactivating a second signal based on the counting information, second rising information, second falling information, and the first falling information; and a control signal driving unit suitable for driving a control signal in response to the first and second signals.

Abstract: A semiconductor memory device includes a column address generation circuit suitable for generating contents addressable memory (CAM) column addresses for duplicated CAM data, a column selection circuit suitable for allocating columns to the duplicated CAM data according to the CAM column addresses, and a plurality of page buffer units, each unit being coupled to a corresponding memory group through the allocated columns, and suitable for storing the duplicated CAM data in the memory groups through the allocated columns. The allocated columns are of arranged sequentially within each memory group in a circular order, and a part of the CAM column addresses represent columns which are physically apart by a predetermined number of columns within a memory group.

Abstract: A control signal generation circuit may include: a counting unit suitable for generating counting information; a first signal generation unit suitable for activating/deactivating a first signal based on the counting information, first rising information, and first falling information; a second signal generation unit suitable for activating/deactivating a second signal based on the counting information, second rising information, second falling information, and the first falling information; and a control signal driving unit suitable for driving a control signal in response to the first and second signals.

Abstract: A memory includes a first memory cell, a bit line corresponding to the first memory cell, at least one second memory cell adjacent to the first memory cell, and a page buffer configured to read data of the first memory cell by precharging the bit line to a voltage level which is decided in response to data of the at least one second memory cell.