Abstract: A memory includes a first memory cell, a bit line corresponding to the first memory cell, at least one second memory cell adjacent to the first memory cell, and a page buffer configured to read data of the first memory cell by precharging the bit line to a voltage level which is decided in response to data of the at least one second memory cell.

Abstract: A semiconductor memory device is operated by, inter alia, sequentially inputting program data to page buffers coupled to selected pages of at least four planes in order to program selected memory cells included in the selected pages; performing a program operation on each of the four planes; performing a program verify operation on each of the four planes; and inputting new program data for next pages to the page buffers coupled to the next pages, after determining the selected pages of at least two of the four planes have passed the program verify operation, while performing the program operations and the program verify operations on the two remaining planes.

Abstract: A nonvolatile memory device including a plurality of memory cells arranged at a region where a word line and a bit line cross each other, a voltage generator configured to generate a program voltage to apply to the word line by increasing the program voltage by an increment whenever a program loop is repeated, a current sensing check unit configured to compare a number of failed memory cells among the memory cells to first and second reference values, and a control logic configured to control the voltage generator to change the increment according to the comparison result of the current sensing check unit.

Abstract: A nonvolatile memory device including a plurality of memory cells arranged at a region where a word line and a bit line cross each other, a voltage generator configured to generate a program voltage to apply to the word line by increasing the program voltage by an increment whenever a program loop is repeated, a current sensing check unit configured to compare a number of failed memory cells among the memory cells to first and second reference values, and a control logic configured to control the voltage generator to change the increment according to the comparison result of the current sensing check unit.

Abstract: Programming a semiconductor memory device includes: performing a program loop using a blind program operation until the selected cell threshold voltages reach a first verification level; upon detecting a cell having the threshold voltage reaching the first verification level, verifying whether a cell having the threshold voltage reached a second verification level higher than the first verification level; upon verifying a cell having the threshold voltage reaching the second verification level, continuously performing program loops on cells having the first verification level as a target level and on cells having the second verification level as a target level; and upon verifying no cell having the threshold voltage reaching the second verification level, performing a program loop on memory cells having a target level higher than the first verification level, after programming the memory cells having the first verification level as the target level.

Abstract: A semiconductor memory device is operated by, inter alia, sequentially inputting program data to page buffers coupled to selected pages of at least four planes in order to program selected memory cells included in the selected pages; performing a program operation on each of the four planes; performing a program verify operation on each of the four planes; and inputting new program data for next pages to the page buffers coupled to the next pages, after determining the selected pages of at least two of the four planes have passed the program verify operation, while performing the program operations and the program verify operations on the two remaining planes.

Abstract: A memory includes a first memory cell, a bit line corresponding to the first memory cell, at least one second memory cell adjacent to the first memory cell, and a page buffer configured to read data of the first memory cell by precharging the bit line to a voltage level which is decided in response to data of the at least one second memory cell.

Abstract: A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level determination signal having a varying data value in response to a selection signal, and a voltage generation unit configured to generate a voltage having a single pulse form or a voltage having a pulse form whose rising edge portion rises in incremental voltage steps in response to the voltage level determination signal outputted from the voltage generation control unit.

Abstract: A flash memory device includes a memory cell array, a peri circuit unit, an I/O controller, and a controller. The memory cell array includes a plurality of memory cells respectively connected to a plurality of bit line pairs and a plurality word lines. The peri circuit unit is configured to program data into the memory cell array or read data stored in the memory cell array in response to a command input through a control bus. The I/O controller is configured to receive data for programming and supply the data to the peri circuit unit in response to a command provided through a data input/output (I/O) bus. The controller is configured to control the I/O controller to perform a voltage setup operation for a program while the data for program is received.

Abstract: Programming a semiconductor memory device includes: performing a program loop using a blind program operation until the selected cell threshold voltages reach a first verification level; upon detecting a cell having the threshold voltage reaching the first verification level, verifying whether a cell having the threshold voltage reached a second verification level higher than the first verification level; upon verifying a cell having the threshold voltage reaching the second verification level, continuously performing program loops on cells having the first verification level as a target level and on cells having the second verification level as a target level; and upon verifying no cell having the threshold voltage reaching the second verification level, performing a program loop on memory cells having a target level higher than the first verification level, after programming the memory cells having the first verification level as the target level.

Abstract: In one aspect of the method of programming a nonvolatile memory device, memory cells selected for a program are determined to belong to a first memory cell group or a second memory cell group based on address information and a program command. According to this determination, to-be-programmed data are input based on information about the number of set data bits, and programming and verification are performed.

Abstract: According to an aspect of a program method of a nonvolatile memory device, a first program operation for programming a first data stored in a first latch may be performed and a cache program signal may be input for inputting a second data to be programmed subsequently. When the cache program signal is input, a determination is made as to whether a first program verify operation is being performed, and if so, the verify operation is stopped, the second data is input, and the first program verify operation is restarted.

Abstract: A method of operating a nonvolatile memory device includes performing a reset operation for setting a level of a program voltage to a first level, performing a program operation and a verification operation on memory cells included in a first page of a first memory block while raising the program voltage from the first level, storing a level of the program voltage, supplied to the first page when memory cells programmed to have threshold voltages with at least a verification voltage are detected during the verification operation, as a second level, while raising the program voltage from the second level, performing the program operation and the verification operation on each of second to last pages of the first memory block, and after completing the program operation for the first memory block, performing the reset operation for setting the level of the program voltage to the first level.

Abstract: A voltage generation circuit comprises a voltage generation control unit configured to output one of a first voltage level determination signal having a fixed data value and a second voltage level determination signal having a varying data value in response to a selection signal, and a voltage generation unit configured to generate a voltage having a single pulse form or a voltage having a pulse form whose rising edge portion rises in incremental voltage steps in response to the voltage level determination signal outputted from the voltage generation control unit.

Abstract: A method of operating a nonvolatile memory device includes performing a reset operation for setting a level of a program voltage to a first level, performing a program operation and a verification operation on memory cells included in a first page of a first memory block while raising the program voltage from the first level, storing a level of the program voltage, supplied to the first page when memory cells programmed to have threshold voltages with at least a verification voltage are detected during the verification operation, as a second level, while raising the program voltage from the second level, performing the program operation and the verification operation on each of second to last pages of the first memory block, and after completing the program operation for the first memory block, performing the reset operation for setting the level of the program voltage to the first level.

Abstract: In a method of determining a flag state of a non-volatile memory device, an arithmetic logic unit of a microcontroller is employed without an additional circuit. The method includes providing n flag state information about n flag cells, resetting an entire flag state information value, sequentially reading first to n flag state information, increasing the entire flag state information value depending on a read result of the first to n flag state information, and determining a flag state by comparing the entire flag state information value and a critical value.

Abstract: In one aspect of the method of programming a nonvolatile memory device, memory cells selected for a program are determined to belong to a first memory cell group or a second memory cell group based on address information and a program command. According to this determination, to-be-programmed data are input based on information about the number of set data bits, and programming and verification are performed.

Abstract: A low power ROM includes a plurality of ROM core groups coupled between a plurality of word lines and bit lines, a word line decoder for selecting a desired word line of the plurality of word lines, a column decoder for selecting a desired bit line of the plurality of bit lines, a common reference voltage generator for generating a common reference voltage, and a plurality of sense amplifiers having the same number as the number of ROM core groups, for comparing an output of the common reference voltage generator and data of a bit line of each ROM core group.

Abstract: According to an aspect of a program method of a nonvolatile memory device, a first program operation for programming a first data stored in a first latch may be performed and a cache program signal may be input for inputting a second data to be programmed subsequently. When the cache program signal is input, a determination is made as to whether a first program verify operation is being performed, and if so, the verify operation is stopped, the second data is input, and the first program verify operation is restarted.

Abstract: In a method of determining a flag state of a non-volatile memory device, an arithmetic logic unit of a microcontroller is employed without an additional circuit. The method includes providing n flag state information about n flag cells, resetting an entire flag state information value, sequentially reading first to n flag state information, increasing the entire flag state information value depending on a read result of the first to n flag state information, and determining a flag state by comparing the entire flag state information value and a critical value.