Abstract: In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics.

Abstract: Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

Abstract: A method of reading data in a non-volatile memory device includes applying a bit line read voltage to a bit line and a selected cell read voltage to a word line, both of which are electrically connected to a selected cell located in a selected string. A first read voltage is applied to word lines electrically connected to first non-selected cells separated from the selected cell in the selected string, and a second read voltage is applied to word lines electrically connected to second non-selected cells adjacent to the selected cell in the selected string. The second read voltage is lower than the first read voltage. A pass voltage is applied to turn on a string select transistor and a ground select transistor, respectively, in the selected string. An electrical signal output from the selected string is compared with a standard signal to read data stored in the selected cell.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: A non-volatile memory device for 2-bit operation and a method of fabricating the same are provided. The non-volatile memory device includes an active region and a gate extending in a word line direction on a semiconductor substrate, and crossing each other repeatedly; a charge storage layer disposed below the gate, and confined at a portion where the gate and the active region cross; a charge blocking layer formed on the charge storage layer; a tunnel dielectric layer formed below the charge storage layer; first and second source/drain regions formed in the active region exposed by the gate; and first and second bit lines crossing the word line direction. The active region may be formed in a first zigzag pattern and/or the gate may be formed in a second zigzag pattern in symmetry with the first zigzag pattern.

Abstract: In a flash memory device, which can maintain an enhanced electric field between a control gate and a storage node (floating gate) and has a reduced cell size, and a method of manufacturing the flash memory device, the flash memory device includes a semiconductor substrate having a pair of drain regions and a source region formed between the pair of drain regions, a pair of spacer-shaped control gates each formed on the semiconductor substrate between the source region and each of the drain regions, and a storage node formed in a region between the control gate and the semiconductor substrate. A bottom surface of each of the control gates includes a first region that overlaps with the semiconductor substrate and a second region that overlaps with the storage node. The pair of spacer-shaped control gates are substantially symmetrical with each other about the source region.

Abstract: Provided is a method of manufacturing a semiconductor device, by which a cell transistor formed on a cell array area of a semiconductor substrate employs a structure in which an electrode in the shape of spacers is used to form a gate and a multi-bit operation is possible using localized bits, and transistors having structures optimized to satisfy different requirements depending upon functions of the transistors can be formed on a peripheral circuit area which is the residual area of the semiconductor substrate. In this method, a cell transistor is formed on the cell array area.

Abstract: A height adjusting apparatus for vehicle seats may include seat side frames provided on both side ends of a seat part of a seat, each of the seat side frames connected to the seat bracket via a front link and a rear link, the support rod coupling the seat side frames to each other, the pinion gear provided on a seat side frame, the rack gear link having on one end thereof a rack gear which engages with an upper end of the pinion gear, and coupled at the other end thereof to a hinge of the front link placed on the seat bracket, so that, when the pinion gear is driven, the rack gear link pulls the seat side frame forwards to lift it up, and the support pin provided on the seat side frame in such a way as to be placed above the rack gear.

Abstract: A non-volatile memory device includes a substrate, resistance patterns, a gate dielectric layer, a gate electrode pattern, a first impurity region and a second impurity region. The substrate has recesses. The recesses are filled with the resistance patterns. The resistance patterns include a material having a resistance that is variable in accordance with a voltage applied thereto. The gate dielectric layer is formed on the substrate. The gate electrode pattern is formed on the gate dielectric layer. The first and second impurity regions are formed in the substrate. The first impurity region and the second impurity region contact side surfaces of the resistance patterns. Further, the resistance patterns, the first impurity region and the second impurity region define a channel region. Thus, the non-volatile memory device may store data using a variable resistance of the resistance patterns so that the non-volatile memory device may have excellent operational characteristics.

Abstract: In a non-volatile memory device allowing multi-bit and/or multi-level operations, and methods of operating and fabricating the same, the non-volatile memory device comprises, in one embodiment: a semiconductor substrate, doped with impurities of a first conductivity type, which has one or more fins defined by at least two separate trenches formed in the substrate, the fins extending along the substrate in a first direction; pairs of gate electrodes formed as spacers at sidewalls of the fins, wherein the gate electrodes are insulated from the semiconductor substrate including the fins and extend parallel to the fins; storage nodes between the gate electrodes and the fins, and insulated from the gate electrodes and the semiconductor substrate; source regions and drain regions, which are doped with impurities of a second conductivity type, and are separately formed at least at surface portions of the fins and extend across the first direction of the fins; and channel regions corresponding to the respective gate

Abstract: In a method of manufacturing a non-volatile memory device, a conductive structure is formed on a substrate. The conductive structure includes a tunnel oxide pattern, a first conductive pattern, a pad oxide pattern and a hard mask pattern. A trench is formed on the substrate using the conductive structure as an etching mask. An inner oxide layer is formed on an inner wall of the trench and sidewalls of the tunnel oxide pattern and the first conductive pattern. The inner oxide layer is cured, thereby forming a silicon nitride layer on the inner oxide layer. A device isolation pattern is formed in the trench, and the hard mask pattern and the pad oxide pattern are removed from the substrate. A dielectric layer and a second conductive pattern are formed on the substrate. Accordingly, the silicon nitride layer prevents hydrogen (H) atoms from leaking into the device isolation pattern.

Abstract: A height adjusting apparatus for vehicle seats may include seat side frames provided on both side ends of a seat part of a seat, each of the seat side frames connected to the seat bracket via a front link and a rear link, the support rod coupling the seat side frames to each other, the pinion gear provided on a seat side frame, the rack gear link having on one end thereof a rack gear which engages with an upper end of the pinion gear, and coupled at the other end thereof to a hinge of the front link placed on the seat bracket, so that, when the pinion gear is driven, the rack gear link pulls the seat side frame forwards to lift it up, and the support pin provided on the seat side frame in such a way as to be placed above the rack gear.

Abstract: A seatback frame for vehicles has a lower cross member that prevents a back pad and a recliner hinge shaft from interfering with each other. The seatback frame includes a back frame and a lower cross member. The lower cross member includes a reinforcing part and a hinge-shaft cover. The back frame is hinged to a seat frame via a recliner hinge shaft. The lower cross member couples both sides of the lower end of the back frame to each other. The reinforcing part has the shape of an embossment which extends in a longitudinal direction of the lower cross member. The hinge-shaft cover is provided on the lower portion of the lower cross member, and is bent to surround the recliner hinge shaft.

Abstract: Provided are a nonvolatile memory device having multi bit storage and a method of manufacturing the same.

Abstract: A method of reading data in a non-volatile memory device includes applying a bit line read voltage to a bit line and a selected cell read voltage to a word line, both of which are electrically connected to a selected cell located in a selected string. A first read voltage is applied to word lines electrically connected to first non-selected cells separated from the selected cell in the selected string, and a second read voltage is applied to word lines electrically connected to second non-selected cells adjacent to the selected cell in the selected string. The second read voltage is lower than the first read voltage. A pass voltage is applied to turn on a string select transistor and a ground select transistor, respectively, in the selected string. An electrical signal output from the selected string is compared with a standard signal to read data stored in the selected cell.

Abstract: In methods of manufacturing a memory device, a tunnel insulation layer is formed on a substrate. A floating gate having a substantially uniform thickness is formed on the tunnel insulation layer. A dielectric layer is formed on the floating gate. A control gate is formed on the dielectric layer. A flash memory device including the floating gate may have more uniform operating characteristics.

Abstract: A non-volatile memory device and a method of forming the same are provided. The non-volatile memory device may include a cell isolation pattern and a semiconductor pattern sequentially stacked on a predetermined or given region of a semiconductor substrate, a cell gate line on the semiconductor pattern and on a top surface of the semiconductor substrate on one side of the cell isolation pattern, a multi-layered trap insulation layer between the cell gate line and the semiconductor substrate, and the cell gate line and the semiconductor pattern, a first impurity diffusion layer in the semiconductor substrate on both sides of the cell gate line and a second impurity diffusion layer in the semiconductor pattern on both sides of the cell gate line.

Abstract: Provided are methods for fabricating semiconductor devices incorporating a fin-FET structure that provides body-bias control, exhibits some characteristic advantages associated with SOI structures, provides increased operating current and/or reduced contact resistance. The methods for fabricating semiconductor devices include forming insulating spacers on the sidewalls of a protruding portion of a first insulation film; forming a second trench by removing exposed regions of the semiconductor substrate using the insulating spacers as an etch mask, and thus forming fins in contact with and supported by the first insulation film. After forming the fins, a third insulation film is formed to fill the second trench and support the fins. A portion of the first insulation film is then removed to open a space between the fins in which additional structures including gate dielectrics, gate electrodes and additional contact, insulating and storage node structures may be formed.

Abstract: A transistor having a gate dielectric layer of partial thickness difference and a method of fabricating the same are provided. The method includes forming a gate dielectric layer having a main portion with a relatively thin thickness formed on a semiconductor substrate, and a sidewall portion with a relatively thick thickness formed on both sides of the main portion. A first gate is formed overlapping the main portion of the gate dielectric layer, and forming a second gate layer covering the sidewall portion of the gate dielectric layer and covering the first gate. The second gate layer is etched, thereby forming second gates patterned with a spacer shape on sidewalls of the first gate. The exposed sidewall portion of the gate dielectric layer is selectively etched using the second gates as a mask, thereby forming a pattern of the gate dielectric layer to be aligned with the second gates. A source/drain is formed in a portion of the semiconductor substrate exposed by the second gates.

Abstract: Conductive structures in an integrated circuit device including an integrated circuit substrate and first conductive layer patterns on the substrate. Second conductive layer patterns are on the substrate extending between respective ones of the first conductive layer patterns. Adjacent ones of the first and second conductive layer patterns are on different horizontal planes relative to the substrate to reduce parasitic capacitance therebetween.