Abstract: A system and method for deploying one or more airbags in a vehicle is provided. The system comprises a passive detection device, an active detection device and a controller. The passive detection device is configured to present one or more passive signals indicative of the motion of the vehicle after the vehicle has experienced an impact. The active detection device is configured to present suspension information related to the vehicle that is indicative of the motion of the vehicle prior to the vehicle experiencing an impact. The controller is configured to predict vehicle impact and deploy the airbags in response to the suspension information and the one or more passive signals.

Abstract: A system for providing post-impact signals in a vehicle is provided. The vehicle includes at least one impact zone with a passive safety sensor positioned at designated sections of the vehicle. The system comprises a plurality of passive safety sensors, a passive safety controller, and an active safety controller. The passive safety controller determines the impact location, impact direction and intensity. The passive safety controller transmits a passive output signal indicative of the impact intensity, impact direction and impact location. The active safety controller stabilizes the vehicle post-impact in response to the passive output signal.

Abstract: The present invention is a light emitting device which uses a specific phosphor powder. The phosphor powder is a combination of cerium (Ce) and lithium aluminum oxide (LiAlO2). They are mixed under a specific range of composition ratio. With the specific phosphor powder applied, the light emitting device has advantages in a low cost, a reduced power consumption, an easy production, a long life, and so on. In addition, a transformation efficiency of the phosphor powder is high and so a light emitting efficiency of the light emitting device is enhanced.

Abstract: A thick gallium nitride (GaN) film is formed on a LiAlO2 substrate through two stages. First, GaN nanorods are formed on the LiAlO2 substrate through chemical vapor deposition (CVD). Then the thick GaN film is formed through hydride vapor phase epitaxy (HVPE) by using the GaN nanorods as nucleus sites. In this way, a quantum confined stark effect (QCSE) becomes small and a problem of spreading lithium element into gaps in GaN on using the LiAlO2 substrate is mended.

Abstract: Techniques for handling dependency conditions, including evil twin conditions, are disclosed herein. An instruction may designate a source register comprising two portions. The source register may be a double-precision register and its two portions may be single-precision portions, each specified as destinations by two other single-precision instructions. Execution of these two single-precision instructions, especially on a register renaming machine, may result in the appropriate values for the two portions of the source register being stored in different physical locations, which can complicate execution of an instruction stream. In response to detecting a potential dependency, one or more instructions may be inserted in an instruction stream to enable the appropriate values to be stored within one physical double precision register, eliminating an actual or potential evil twin dependency.

Abstract: Various techniques for mitigating dependencies between groups of instructions are disclosed. In one embodiment, such dependencies include “evil twin” conditions, in which a first floating-point instruction has as a destination a first portion of a logical floating-point register (e.g., a single-precision write), and in which a second, subsequent floating-point instruction has as a source the first portion and a second portion of the same logical floating-point register (e.g., a double-precision read). The disclosed techniques may be applicable in a multithreaded processor implementing register renaming. In one embodiment, a processor may enter an operating mode in which detection of evil twin “producers” (e.g., single-precision writes) causes the instruction sequence to be modified to break potential dependencies. Modification of the instruction sequence may continue until one or more exit criteria are reached (e.g., committing a predetermined number of single-precision writes).

Abstract: A lithium aluminum oxide (LiAlO2) substrate suitable for a zinc oxide (ZnO) buffer layer is found. The ZnO buffer layer is grown on the LiAlO2 substrate. Because the LiAlO2 substrate has a similar structure to that of the ZnO buffer layer, a quantum confined stark effect (QCSE) is effectively eliminated. And a photoelectrical device made with the present invention, like a light emitting diode, a piezoelectric material or a laser diode, thus obtains an enhanced light emitting efficiency.

Abstract: A thick gallium nitride (GaN) film is formed on a LiAlO2 substrate through two stages. First, GaN nanorods are formed on the LiAlO2 substrate through chemical vapor deposition (CVD). Then the thick GaN film is formed through hydride vapor phase epitaxy (HVPE) by using the GaN nanorods as nucleus sites. In this way, a quantum confined stark effect (QCSE) becomes small and a problem of spreading lithium element into gaps in GaN on using the LiAlO2 substrate is mended.

Abstract: In some embodiments, an electron multiplier includes a neutron-sensitive composition having, in weight percent, approximately 30% to approximately 60% silicon oxide, approximately 20% to approximately 60% lead oxide, and approximately 1% to approximately 15% boron-10 enriched boron oxide. The composition is capable of interacting with neutrons to form an electron cascade. The electron multiplier can be in the form of a microchannel plate, a microfiber plate, or a microsphere plate.

Abstract: In accordance with one embodiment, an enhanced chip multiprocessor permits an L1 cache to request ownership of a data line from a shared L2 cache. A determination is made whether to deny or grant the request for ownership based on the sharing of the data line. In one embodiment, the sharing of the data line is determined from an enhanced L2 cache directory entry associated with the data line. If ownership of the data line is granted, the current data line is passed from the shared L2 to the requesting L1 cache and an associated enhanced L1 cache directory entry and the enhanced L2 cache directory entry are updated to reflect the L1 cache ownership of the data line. Consequently, updates of the data line by the L1 cache do not go through the shared L2 cache, thus reducing transaction pressure on the shared L2 cache.

Abstract: Architecture that employs a combination of in-band signaling (e.g., DTMF) with speech recognition to deliver usability improvements. The in-band signaling allows the user to indicate to the system when a barge-in operation is occurring and/or when to start listening to subsequent speech input and optionally, when to stop listening for further speech input. The in-band signaling can be utilized during a telephone call and using wireline and wireless telephones. Moreover, the architecture can be incorporated at the platform level requiring little, if any, application changes to support the new mode of operation.

Abstract: A lockable vehicle steering-wheel tilting assembly (LVWTA) (10) that functions in combination with and improves an existing vehicle steering-wheel tilting assembly. The LVWTA (10) includes an inward structure (12) that attaches to a steering-wheel column (102) and an outward structure (32) that is pivotally attached to the inward structure (12) and that it is attached to a vehicle-steering wheel (100). The LVWTA (10) is designed to position the steering wheel (100) in either a safe steering configuration or in a driver-exit configuration in which position the vehicle cannot be safely steered. The LVWTA (10) improves an existing steering wheel tilting assembly by removably inserting and attaching a locking insert (70) to the inward structure (12). When the locking insert (70) is attached and locked by means of a cylindrical key lock (90), the LVWTA (10) cannot be placed into the safe steering configuration.

Abstract: Maintaining a cache of indications of exclusively-owned coherence state for memory space units (e.g., cache line) allows reduction, if not elimination, of delay from missing store operations. In addition, the indications are maintained without corresponding data of the memory space unit, thus allowing representation of a large memory space with a relatively small missing store operation accelerator. With the missing store operation accelerator, a store operation, which misses in low-latency memory (e.g., L1 or L2 cache), proceeds as if the targeted memory space unit resides in the low-latency memory, if indicated in the missing store operation accelerator. When a store operation misses in low-latency memory and hits in the accelerator, a positive acknowledgement is transmitted to the writing processing unit allowing the store operation to proceed. An entry is allocated for the store operation, the store data is written into the allocated entry, and the target of the store operation is requested from memory.

Abstract: A charged device model (CDM) electrostatic discharge (ESD) testing is carried out at wafer level. Wafer CDM pulses are repeatedly applied and monitored. The wafer CDM (WCDM) pulses are accomplished with a probe-mounted printed-circuit board and a high-frequency transformer that captures fast CDM pulses. Modeling of CDM and WCDM in the time and frequency domain illustrates the dominant effects, and shows that WCDM can reproduce all the major phenomena of package-level CDM testing.

Abstract: A system and method for reducing branch misprediction penalty. In response to detecting a mispredicted branch instruction, circuitry within a microprocessor identifies a predetermined condition prior to retirement of the branch instruction. Upon identifying this condition, the entire corresponding pipeline is flushed prior to retirement of the branch instruction, and instruction fetch is started at a corresponding address of an oldest instruction in the pipeline immediately prior to the flushing of the pipeline. The correct outcome is stored prior to the pipeline flush. In order to distinguish the mispredicted branch from other instructions, identification information may be stored alongside the correct outcome. One example of the predetermined condition being satisfied is in response to a timer reaching a predetermined threshold value, wherein the timer begins incrementing in response to the mispredicted branch detection and resets at retirement of the mispredicted branch.

Abstract: A method for pre-fetching data. The method includes obtaining a pre-fetch request. The pre-fetch request identifies new data to pre-fetch from memory and store in a cache. The method further includes identifying a set in the cache to store the new data and identifying a value of a hotness indicator for the set. The hotness indicator value defines a number of replacements of at least one line in the set. The method further includes determining whether the value of the hotness indicator exceeds a predefined threshold, and storing the new data in the set when the value of the hotness indicator does not exceed the pre-defined threshold.

Abstract: A multithreading processor achieves a very large lookahead instruction window by allowing non-sequential fetch and processing of the dynamic instruction stream. A speculative thread is spawned at a specified point in the dynamic instruction stream and the instructions subsequent to the specified point are speculatively executed so that these instructions are fetched and issued out of sequential order. Very minimal modifications to existing processor design of a multithreading processor are required to achieve the very large lookahead instruction window. The modifications include changes to the control logic of the issue unit, only three additional bits in the register scoreboard.

Abstract: A method for prefetching data and/or instructions from a main memory to a cache memory may include generating control flow information by storing respective information for each retired branch instruction. The method may further include storing respective one or more cache miss addresses for each retired instruction that incurs one or more cache misses, with the respective one or more cache miss addresses corresponding respectively to the one or more cache misses. A correlation table may be maintained based on the generated control flow information and the stored cache miss addresses. Each respective correlation table entry may correspond to a respective index, and may contain a respective tag and a respective correlation list. The correlation list may consist of a specified number of cache miss addresses that most frequently follow the cache miss address used in generating the index to which the respective correlation table entry corresponds.

Abstract: A system and method for detecting a rollover of a vehicle that includes at least one wheel reaction force sensing device for transmitting wheel reaction force signals indicative of an amount of force exerted on at least one wheel of the vehicle is provided. The system includes a controller operably coupled to the at least one wheel reaction force sensing device and including at least one accelerometer sensor for transmitting acceleration signals. The controller is configured to determine a first force index in response to the wheel reaction force signals, determine a first lateral acceleration of the vehicle in response to the acceleration signals, compare the first force index to a threshold force index and the first lateral acceleration to a threshold lateral acceleration, and deploy a restraint system based on the comparison.

Abstract: A computer processor and a method of using the computer processor take advantage of information in the event address register of the computer processor by saving information from the event address register to an event address register history buffer. Thus, the event address register history buffer includes a cluster of events associated with execution of a computer program. The cluster of events is analyzed and the computer program modified, either statically or dynamically, to eliminate or at least ameliorate the effects of such events in further execution of the computer program.