Abstract: A method and system for efficient implementation of a large store buffer within a processor includes a store buffer within a processor having a first component configured to hold a plurality of younger stores requested by the processor and a second component configured to hold a plurality of older stores. The first component is implemented as a small content addressable memory (CAM) and the second component includes a first-in-first-out (FIFO) buffer to hold the data and addresses of the plurality of older stores and an address disambiguator to hold the addresses of each of the plurality of older stores found in the FIFO buffer. The processor uses the small CAM to perform most of the store-to-load forwarding in a fast and efficient way thereby enhancing processor performance.

Abstract: A system and method for performing side impact sensing in a vehicle including at least one side impact zone is provided. The system comprises a controller and at least one crash signature sensor. The controller is configured to deploy one or more safety restraints in response to at least one crash signature signal. The one crash signature sensor is positioned in the side impact zone. The crash signature sensor is configured to detect an impact with an object at the side impact zone. The crash signature sensor is further configured to generate the crash signature signal which corresponds to measured structural impact energy of the vehicle in the side impact zone deformed by the impact at frequencies above 2 kHz.

Abstract: A method for making a free-standing, single crystal, aluminum gallium nitride (AlGaN) wafer includes forming a single crystal AlGaN layer directly on a single crystal LiAlO2 substrate using an aluminum halide reactant gas, a gallium halide reactant gas, and removing the single crystal LiAlO2 substrate from the single crystal AlGaN layer to make the free-standing, single crystal AlGaN wafer. Forming the single crystal AlGaN layer may comprise depositing AlGaN by vapor phase epitaxy (VPE) using aluminum and gallium halide reactant gases and a nitrogen-containing reactant gas. The growth of the AlGaN layer using VPE provides commercially acceptable rapid growth rates. In addition, the AlGaN layer can be devoid of carbon throughout. Because the AlGaN layer produced is high quality single crystal, it may have a defect density of less than about 107cm?2.

Abstract: The storage of data line in one or more L1 caches and/or a shared L2 cache of a chip multiprocessor is dynamically optimized based on the sharing of the data line. In one embodiment, an enhanced L2 cache directory entry associated with the data line is generated in an L2 cache directory of the shared L2 cache. The enhanced L2 cache directory entry includes a cache mask indicating a storage state of the data line in the one or more L1 caches and the shared L2 cache. In some embodiments, where the data line is stored in the shared L2 cache only, a portion of the cache mask indicates a storage history of the data line in the one or more L2 caches.

Abstract: One embodiment of the present invention provides a system that selectively executes different versions of executable code for the same source code. During operation, the system first receives an executable code module which includes two or more versions of executable code for the same source code, wherein the two or more versions of the executable code are optimized in different ways. Next, the system executes the executable code module by first evaluating a test condition, and subsequently executing a specific version of the executable code based on the outcome of the evaluation, so that the execution is optimized for the test condition.

Abstract: One embodiment of the present invention provides a system that improves the effectiveness of prefetching during execution of instructions in scout mode. Upon encountering a non-data dependent stall condition, the system performs a checkpoint and commences execution of instructions in scout mode, wherein instructions are speculatively executed to prefetch future memory operations, but wherein results are not committed to the architectural state of a processor. When the system executes a load instruction during scout mode, if the load instruction causes a lower-level cache miss, the system allows the load instruction to access a higher-level cache. Next, the system places the load instruction and subsequent dependent instructions into a deferred queue, and resumes execution of the program in scout mode.

Abstract: A slave device adapted to couple to a master processor and including an error handler and a communication controller. The error handler is configured to detect errors internal to the slave device and, in response to detecting at least one error and independent of the master processor, configured to select an error recovery operation based on the at least one detected error and to initiate and perform the selected error recovery operation. The communication controller is configured to communicate with the master processor according to a master/slave protocol, and configured to maintain the master/slave protocol during performance of the selected error recovery operation by the error handler.

Abstract: In some embodiments, an electron multiplier includes a neutron-sensitive composition having, in weight percent, approximately 30% to approximately 60% silicon oxide, approximately 20% to approximately 60% lead oxide, and approximately 1% to approximately 15% boron-10 enriched boron oxide. The composition is capable of interacting with neutrons to form an electron cascade. The electron multiplier can be in the form of a microchannel plate, a microfiber plate, or a microsphere plate.

Abstract: A method is disclosed that uses a non-coherent store instruction to reduce inter-thread communication latency between threads sharing a level one write-through cache. When a thread executes the non-coherent store instruction, the level one cache is immediately updated with the data value. The data value is immediately available to another thread sharing the level-one write-through cache. A computer system having reduced inter-thread communication latency is disclosed. The computer system includes a first plurality of processor cores, each processor core including a second plurality of processing engines sharing a level one write-through cache. The level one caches are connected to a level two cache via a crossbar switch. The computer system further implements a non-coherent store instruction that updates a data value in the level one cache prior to updating the corresponding data value in the level two cache.

Abstract: A system for providing post-impact signals in a vehicle is provided. The vehicle includes at least one impact zone with a passive safety sensor positioned at designated sections of the vehicle. The system comprises a plurality of passive safety sensors, a passive safety controller, and an active safety controller. The passive safety controller determines the impact location, impact direction and intensity. The passive safety controller transmits a passive output signal indicative of the impact intensity, impact direction and impact location. The active safety controller stabilizes the vehicle post-impact in response to the passive output signal.

Abstract: A multi-stride prefetcher includes a recurring prefetch table that in turn includes a stream table and an index table. The stream table includes a valid field and a tag field. The stream table also includes a thread number field to help support multi-threaded processor cores. The tag field stores a tag from an address associated with a cache miss. The index table includes fields for storing information characterizing a state machine. The fields include a learning bit. The multi-stride prefetcher prefetches data into a cache for a plurality of streams of cache misses, each stream having a plurality of strides.

Abstract: A restraint control system (40) for an automotive vehicle (10) is illustrated with a first sensor such as a door cavity pressure sensor (28) and a second sensor such as an accelerometer (30). A restraint device (54) is coupled to a controller (52) that controls the operation of the restraint device in response to the first sensor (28) and the second sensor (30). When either the signal from the first sensor or the signal from the second sensor is above a first or second threshold, respectively, the two signals are compared. In response to the comparison, the restraint device (54) is deployed.

Abstract: One embodiment of the present invention provides a system that performs register file checkpointing to support speculative execution within a processor. During operation, the system commences speculative execution of a program from a point of speculation, at which the outcome of a long latency instruction is speculatively predicted. During this speculative execution, registers are updated by checkpointing an old value of the register, if the register has not already been checkpointed, and then updating the architectural state of the register with the new value. In this way, only registers that are updated during the speculative execution are checkpointed, instead of checkpointing all of the architectural registers prior to commencing speculative execution.

Abstract: A system and method for deploying one or more airbags in a vehicle is provided. The system comprises a passive detection device, an active detection device and a controller. The passive detection device is configured to present one or more passive signals indicative of the motion of the vehicle after the vehicle has experienced an impact. The active detection device is configured to present suspension information related to the vehicle that is indicative of the motion of the vehicle prior to the vehicle experiencing an impact. The controller is configured to predict vehicle impact and deploy the airbags in response to the suspension information and the one or more passive signals.

Abstract: A dynamic prediction is made whether a load instruction will miss a cache. Data is prefetched for the load instruction when a cache miss is predicted. Thus, the prefetch is only performed if a trigger event correlated with a cache miss for that load instruction is detected. This selective execution of the prefetches for a particular load instruction improves processor utilization and performance.

Abstract: Systems and related methods are described for handling one or more resource requests. A protocol engine receives a resource request in accordance with a prescribed protocol, and a classification engine determines a desired class of service for the request. An analysis engine optionally analyzes the request, and, responsive thereto, determines a desired sub-class of service for the request. A policy engine then allocates a resource to the request responsive to one or both of the desired class of service, and the desired sub-class of service.

Abstract: A restraint control system (40) for an automotive vehicle (10) is illustrated with a first sensor such as a door cavity pressure sensor (28) and a second sensor such as an accelerometer (30). A restraint device (54) is coupled to a controller (52) that controls the operation of the restraint device in response to the first sensor (28) and the second sensor (30). When either the signal from the first sensor or the signal from the second sensor is above a first or second threshold, respectively, the two signals are compared. In response to the comparison, the restraint device (54) is deployed.

Abstract: A light emitting diode (LED) is made. The LED had a LiAlO2 substrate and a GaN layer. Between them, there is a zinc oxide (ZnO) layer. Because GaN and ZnO have a similar. Wurtzite structure, GaN can easily grow on ZnO. By using the ZnO layer, the GaN layer is successfully grown as a single crystal thin film on the LiAlO2 substrate. Thus, GaN defect density is reduced and lattice match is obtained to have a good crystal interface quality and an enhanced light emitting efficiency of a device thus made.

Abstract: The present invention is a light emitting device which uses a specific phosphor powder. The phosphor powder is a combination of cerium (Ce) and lithium aluminum oxide (LiAlO2). They are mixed under a specific range of composition ratio. With the specific phosphor powder applied, the light emitting device has advantages in a low cost, a reduced power consumption, an easy production, a long life, and so on. In addition, a transformation efficiency of the phosphor powder is high and so a light emitting efficiency of the light emitting device is enhanced.

Abstract: A lithium aluminum oxide (LiAlO2) substrate suitable for a zinc oxide (ZnO) buffer layer is found. The ZnO buffer layer is grown on the LiAlO2 substrate. Because the LiAlO2 substrate has a similar structure to that of the ZnO buffer layer, a quantum confined stark effect (QCSE) is effectively eliminated. And a photoelectrical device made with the present invention, like a light emitting diode, a piezoelectric material or a laser diode, thus obtains an enhanced light emitting efficiency.