Abstract: A structure of energy storage device, including a plurality of rechargeable batteries disposed in a row with a distance to each other, and a heat dissipating structure firmly inserted accordingly between the rechargeable batteries. The heat dissipating structure is a heat dissipating medium of the energy storage device.

Abstract: A control system for an electrical power generation system (EPGS) provides overload protection without disconnecting a generator of the EPGS from an excessive electrical load. Available engine power and current levels of the electrical load are continuously measured. A command voltage is calculated that corresponds to a voltage required to sustain with the maximum available power. Output voltage of a generator of the EPGS is controlled at the calculated command voltage so that a power limit of the engine is not exceeded during electrical overload conditions.

Abstract: A package substrate including a circuit board, a reinforcing plate and at least one conductive channel is provided. A first surface of the reinforcing plate is disposed on the circuit board for resisting the warpage of the circuit board. The reinforcing plate has an opening corresponding to a first contact of the circuit board exposed thereon. In addition, one end of the conductive channel is located in the opening and electrically connected to the first contact, and the other end of the conductive channel is located on a second surface of the reinforcing plate to form a bonding pad.

Abstract: An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.

Abstract: A circuit board structure comprising a composite layer, a fine circuit pattern and a patterned conductive layer is provided. The fine circuit pattern is inlaid in the composite layer, and the patterned conductive layer is disposed on a surface of the composite layer. After fine circuit grooves are formed on the surface of the composite layer, conductive material is filled into the grooves to form the fine circuit pattern inlaid in the composite layer. Since this fine circuit pattern has relatively fine line width and spacing, the circuit board structure has a higher wiring density.

Abstract: An electrical interconnecting structure suitable for a circuit board is provided. The electrical interconnecting structure includes a core, an ultra fine pattern, and a patterned conductive layer. The core has a surface, and the ultra fine pattern is inlaid in the surface of the core. The patterned conductive layer is disposed on the surface of the core and is partially connected to the ultra fine pattern. Since the ultra fine pattern of the electrical interconnecting structure is inlaid in the surface of the core and is partially connected to the patterned conductive layer located on the surface of the core.

Abstract: A circuit board and process thereof are provided. The circuit board includes a dielectric layer, an active circuit, and two shielding circuits. The dielectric layer has an active surface. The active circuit is disposed on the active surface, and the shielding circuits are respectively disposed on two sides of the active circuit. The height of the shielding circuits is larger than the height of the active circuit.

Abstract: The present invention relates to a power management system comprising at least one power management subsystem. Each power management subsystem comprises a first power module coupled to a first load and comprising at least one first power supply for supplying power to the first load; a second power module coupled to a second load and comprising at least one second power supply, wherein at least one second power supply is retractably installed in the second power module and selectively coupled to the second load; and a pass-through module comprising at least one pass-through unit retractably installed in the second power module to replace with the at least one second power supply and selectively connecting the first power module to the second load for allowing the first power module to supply power to the second load.

Abstract: A power converter system supplies power to one or more loads. The power converter system comprises at least one power converter operating at a desired efficiency; and a power storage system coupled to the at least one power converter for receiving power supplied from the at least one power converter and storing power therein when the at least one power converter operates at an efficiency that is below the desired efficiency.

Abstract: A circuit board and process thereof are provided. The circuit board includes a dielectric layer, a main circuit, and two shielding circuits. The dielectric layer has an active surface. The main circuit is embedded in the dielectric layer and the shielding circuits are disposed at the dielectric layer. The shielding circuits are respectively located at two sides of the main circuit. The thickness of the shielding circuits is larger than the thickness of the main circuit.

Abstract: A process for fabricating a circuit board is provided. In the process, first, a circuit substrate including an insulation layer and at least a pad contacting the insulation layer is provided. Next, a barrier material layer is formed on the circuit substrate. The barrier material layer completely covers the insulation layer and the pad. Then, at least one conductive bump is formed on the barrier material layer. The conductive bump is opposite to the pad, and the material of the barrier material layer is different from the material of the conductive bump. Next, a portion of the barrier material layer is removed by using the conductive bump as a mask, so as to expose the surface of the insulation layer and to form a barrier connected between the conductive bump and the pad.

Abstract: A control system for an electrical power generation system (EPGS) provides overload protection without disconnecting a generator of the EPGS from an excessive electrical load. Available engine power and current levels of the electrical load are continuously measured. A command voltage is calculated that corresponds to a voltage required to sustain with the maximum available power. Output voltage of a generator of the EPGS is controlled at the calculated command voltage so that a power limit of the engine is not exceeded during electrical overload conditions.

Abstract: An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.

Abstract: The present disclosure provides an image sensor semiconductor device. A semiconductor substrate having a first-type conductivity is provided. A plurality of sensor elements is formed in the semiconductor substrate. An isolation feature is formed between the plurality of sensor elements. An ion implantation process is performed to form a doped region having the first-type conductivity substantially underlying the isolation feature using at least two different implant energy.

Abstract: Methods and apparatus are provided for reducing and/or substantially eliminating sensitivity mismatch of acoustic receivers used with acoustic sources to determine acoustic properties of geologic formations as a logging tool traverses the formations. Methods are directed to detecting waveform arrival times at receivers, determining places in a well where arrival times of waves are substantially the same at a plurality of receivers, and estimating effective receiver sensitivities and equalization factors using Stoneley wave amplitudes and windowed deconvolution of Stoneley waves. Methods are further directed to correcting wave amplitudes using estimated effective receiver sensitivities and equalization factors for receivers.

Abstract: A package substrate including a circuit board, a reinforcing plate and at least one conductive channel is provided. A first surface of the reinforcing plate is disposed on the circuit board for resisting the warpage of the circuit board. The reinforcing plate has an opening corresponding to a first contact of the circuit board exposed thereon. In addition, one end of the conductive channel is located in the opening and electrically connected to the first contact, and the other end of the conductive channel is located on a second surface of the reinforcing plate to form a bonding pad.

Abstract: An embedded chip package process is provided. First, a chip is connected to a first circuit layer on a carrier, and then a cover plate is pressed onto a dielectric material layer to make the chip embedded in the dielectric material layer so that a circuit board with an embedded chip is formed. The chip has at least a bump electrically connected to a bonding pad of the first circuit layer through a solder. With enhanced reliability and alignment in chip bonding, the flip-chip bonding process replaces the conventional method of Laser drilling and circuit fabrication.

Abstract: An embedded chip package process is disclosed. First, a first substrate having a first patterned circuit layer thereon is provided. Then, a first chip is disposed on the first patterned circuit layer and electrically connected to the first patterned circuit layer. A second substrate having a second patterned circuit layer thereon is provided. A second chip is disposed on the second patterned circuit layer and electrically connected to the second patterned circuit layer. Afterwards, a dielectric material layer is formed and covers the first chip and the first patterned circuit layer. Then, a compression process is performed to cover the second substrate over the dielectric material layer so that the second patterned circuit layer and the second chip on the second substrate are embedded into the dielectric material layer.

Abstract: A fabrication process of a conductive column suitable for a fabrication of a circuit board. The circuit board comprises a dielectric layer. A first blind hole is formed in the dielectric layer from a second surface opposite to the first surface, wherein the blind end of the first blind hole connects to the blind end of the second blind hole. The first blind hole and the second blind hole constitute a through hole. The through hole is formed in an hourglass shape such that an inner diameter of the through hole near the first or the second surface is substantially larger than an inner diameter of the through hole near a middle portion of the through hole. A conductive material is filled in the though hole to form a conductive column.

Abstract: A handheld computer enables an operator to authenticate an ID, determine if an ID holder is above a minimum age, and enables the collection of data about the ID holder if the ID holder is determined to be above the minimum age. The computer also displays an optional video after the age verification process is completed.