Abstract: Structures that include resistive memory elements and methods of forming a structure that includes resistive memory elements. The structure comprises a first plurality of resistive memory elements including a first plurality of bottom electrodes, a first top electrode, and a first switching layer between the first top electrode and the first plurality of bottom electrodes. The structure further comprises a second plurality of resistive memory elements including a second plurality of bottom electrodes, a second top electrode, and a second switching layer between the second top electrode and the second plurality of bottom electrodes. The first top electrode is shared by the first plurality of resistive memory elements, and the second top electrode is shared by the second plurality of resistive memory elements.

Abstract: The present disclosure relates to semiconductor structures and, more particularly, to a capacitor integrated with a memory element of a memory cell and methods of manufacture. The structure includes: at least one memory cell comprising a memory element with a top conductor material; and a capacitor connected to the memory element by the top conductor material.

Abstract: A structure includes an array of nonvolatile memory cells, wordlines and bitlines connected to the nonvolatile memory cells, sense amplifiers connected to the nonvolatile memory cells, and reference cells connected to the sense amplifiers. Each of the reference cells has a transistor connected to a variable resistor, one of the wordlines, a reference bitline separate from the bitlines, and the sense amplifiers.

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

Abstract: A controller that is associated with a pump system causes a power ramp rate of a motor of the pump system to have an initial power ramp rate. The controller monitors, after causing the power ramp rate of the motor to have the initial power ramp rate, a frequency of a power bus. One or more power sources provide power to the pump system via the power bus. The controller causes, based on monitoring the frequency of the power bus, the power ramp rate of the motor to be modified.

Abstract: Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.

Abstract: The present disclosure relates to memory devices and, more particularly, to bias voltage generation circuit for memory devices and methods of operation. The voltage generation circuit includes: an internal voltage generator which providing a bias voltage to at least one internal node of a bias voltage generation circuitry; and at least one pre-charging circuitry providing a predefined bias voltage to at least one internal node including a distributed network of local drivers.

Abstract: In some implementations, a controller may obtain a setting for a target discharge pressure associated with a fluid pump driven by a motor that is controlled by a variable frequency drive (VFD). The target discharge pressure may be for use in a pressure test of a system that includes the fluid pump. The controller may determine a target torque for the motor that achieves the target discharge pressure. The controller may cause, via the VFD and in connection with the pressure test, adjustment to a speed of the motor to achieve the target torque for the motor.

Abstract: In some implementations, a controller may obtain a setting for a maximum discharge pressure associated with a fluid pump that is to be allowed during a hydraulic fracturing operation. The fluid pump may be driven by a motor that is controlled by a variable frequency drive (VFD). The controller may determine a maximum torque for the motor that achieves the maximum discharge pressure. The controller may cause, via the VFD, adjustment to a speed of the motor to maintain a torque of the motor at or below the maximum torque for the motor.

Abstract: Stand-alone interbody fusion devices for engagement between adjacent vertebrae. The stand-alone interbody fusion devices may include a spacer and one or more inserts or members coupled to the spacer. The inserts or members may be configured and designed to provide the apertures which are designed to retain bone fasteners, such as screws, and secure the implant to the adjacent vertebrae.

Abstract: In some implementations, a controller may monitor an available power supply of at least one power source for a system for hydraulic fracturing, and a current power demand of the system. The controller may determine, based on monitoring the available power supply and the current power demand, whether a relationship between the current power demand and the available power supply is indicative of an impending power failure. The controller may cause, based on determining that the relationship between the current power demand and the available power supply indicates the impending power failure, reduction of flow rates of one or more fluid pumps of the system to reduce the current power demand.

Abstract: Stand-alone interbody fusion devices for engagement between adjacent vertebrae. The stand-alone interbody fusion devices may include a spacer and one or more inserts or members coupled to the spacer. The inserts or members may be configured and designed to provide the apertures which are designed to retain bone fasteners, such as screws, and secure the implant to the adjacent vertebrae.

Abstract: Embodiments of the present disclosure provide an apparatus including a memory array including a plurality of sub-arrays. A plurality of temporary storage units (TSUs) is coupled to the plurality of sub-arrays. Each TSU indicates whether the respective sub-array is undergoing one of a read operation and a write operation. A control circuit is coupled to each of the plurality of sub-arrays through a data bus. The control circuit transmits a read pulse or a write pulse as a first pulse with a delay in response to the sub-array undergoing the read operation or the write operation and transmits, instantaneously, the first pulse to one of the plurality of sub-arrays in response to the sub-array not undergoing the read operation or the write operation.

Abstract: Embodiments of the present disclosure provide an apparatus including a memory array including a plurality of sub-arrays. A plurality of temporary storage units (TSUs) is coupled to the plurality of sub-arrays. Each TSU indicates whether the respective sub-array is undergoing one of a read operation and a write operation. A control circuit is coupled to each of the plurality of sub-arrays through a data bus. The control circuit transmits a read pulse or a write pulse as a first pulse with a delay in response to the sub-array undergoing the read operation or the write operation and transmits, instantaneously, the first pulse to one of the plurality of sub-arrays in response to the sub-array not undergoing the read operation or the write operation.

Abstract: Interspinous process implants are disclosed. Also disclosed are systems and kits including such implants, methods of inserting such implants, and methods of alleviating pain or discomfort associated with the spinal column.

Abstract: Disclosed is a memory structure with reference-free single-ended sensing. The structure includes an array of non-volatile memory (NVM) cells (e.g., resistance programmable NVM cells) and a sense circuit connected to the array via a data line and a column decoder. The sense circuit includes field effect transistors (FETs) connected in parallel between an output node and a switch and inverters connected between the data line and the gates of the FETs, respectively. To determine the logic value of a stored bit, the inverters are used to detect whether or not a voltage drop occurs on the data line within a predetermined period of time. Using redundant inverters to control redundant FETs connected to the output node increases the likelihood that the occurrence of the voltage drop will be detected and captured at the output node, even in the presence of process and/or thermal variations. Also disclosed is a sensing method.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: A resilient core is positioned between bony projections which are offset from a principal load bearing region of a spinal joint. Shaped projections extend from the core, and engage the bony projections by conforming to anatomical landmarks, and may be fastened to the bony projections. During flexion of the joint, the core absorbs some of the force of compression, and limits an extent to which the joint may compress. If the shaped projections are connected to the bony projections, extension of the joint is inhibited by the projections and the core, limiting the extent to which the joint may be distracted. In this manner, healing is fostered, and a weakened or damaged joint is protected from excessive movement.

Abstract: An unchamfered piston ring that is pre-treated by grit blasting to a defined roughness, followed by PVD coating with a metal nitride to a thickness of at least 10 ?m, leaving peaks and valleys in the coated piston ring. The coated piston ring is then lapped to remove the peaks without penetrating the coating, so that valleys and plateaus remain in the coated surface. The resulting piston ring exhibits superior coating retention due to the increased surface area created by the grit blasting, and yet also superior performance, as the cavities remaining increase the porosity of the coating and thus enhance the lubrication of the ring.

Abstract: The present disclosure relates to a structure including a latch circuit, a first non-volatile field effect transistor (FET) connecting to a first side of the latch circuit and a bit line, and a second non-volatile field effect transistor (FET) connecting to a second side of the latch circuit and a complementary bit line.