Abstract: A joint spacer therapeutically maintains separation of bones of a joint. A carriage is slideably retained within the frame and has at least one ramped surface. An actuator screw is threadably engaged with the frame, and rotatably connected to the carriage, to cause the carriage to slideably move within the frame when the actuator screw is rotated. First and second endplates engage the bones of the joint, and each has at least one ramped surface that is mateable with the ramped surface of the carriage, whereby when the carriage is slideably moved by rotation of the actuator screw, the endplates ramped surface slides against the carriage ramped surface to cause the endplates to move along an axis transverse to the longitudinal axis of the frame, to increase the height of the spacer. Piercing elements are connected to the carriage to pierce bone of the joint when the carriage is moved.

Abstract: A piston ring that is pre-treated by grit blasting to a defined roughness, followed by PVD coating with a metal nitride to a thickness of at least 10 ?m, leaving peaks and valleys in the coated piston ring. The coated piston ring is then lapped to remove the peaks without penetrating the coating, so that valleys and plateaus remain in the coated surface. The resulting piston ring exhibits superior coating retention due to the increased surface area created by the grit blasting, and yet also superior performance, as the cavities remaining increase the porosity of the coating and thus enhance the lubrication of the ring.

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.

Abstract: An intervertebral prosthetic implant having a first endplate having a first surface configured to substantially engage with a first vertebral body and a second surface having an extension with a concave contact surface, the concave contact surface being spaced apart from the second surface. A second endplate is provided with a first surface configured to substantially engage with a second vertebral body and a second surface comprising a convex contact surface, and the second endplate having a securing element positioned along and above the second surface defining a first and second window on opposing sides of the second surface. The securing element extends along the width and length of the lower endplate and configured with an access hole. An extension portion extends from the first surface of the first endplate through the access hole of the securing element and contacts the second surface of the second endplate.

Abstract: Stand-alone interbody fusion devices for engagement between adjacent vertebrae. The stand-alone interbody fusion devices may include a spacer and one or more inserts or members coupled to the spacer. The inserts or members may be configured and designed to provide the apertures which are designed to retain bone fasteners, such as screws, and secure the implant to the adjacent vertebrae.

Abstract: The described disclosure presents embodiments of an efficient shortwave radio technique using a network of multiple sites located in and around an operating region (e.g., continental USA), calibrated distributed beacons, a detailed knowledge of ionospheric behavior, and sophisticated operational tools and software, that geo-locates targets without depending on satellites. The embodiments of the technique described herein, for example, accurately may locate a target by utilizing remote field units, a network of radio receive sites, receivers that accept and time stamp pertinent signals, demodulators that recognize and extract meaningful data from received signals, communications from all receive sites to a Network Operations Center (NOC), communications from NOC to field units to keep shortwave channel choices relevant and effective, and a processor within the NOC that analyzes and evaluates data.

Abstract: The present disclosure relates to a structure including a non-fixed read-cell circuit configured to switch from a first state to a second state based on a state of a memory cell to generate a sensing margin.

Abstract: Embodiments of the disclosure provide a system for providing a true random number (TRN) or physically unclonable function (PUF), including: an array of voltage controlled magnetic anisotropy (VCMA) cells; a voltage pulse tuning circuit for generating and applying a stochastically tuned voltage pulse to the VCMA cells in the array of VCMA cells, wherein the stochastically tuned voltage pulse has a magnitude and duration that provides a 50%-50% switching distribution of the VCMA cells in the array of VCMA cells; and a bit output system for reading a state of each of the VCMA cells in the array of VCMA cells to provide a TRN or PUF.

Abstract: An intervertebral spacer and stabilization implant includes a plate having sockets configured for retaining a fastener passable through the socket and into an adjacent vertebral body. One or more connecting projections extend from a side of the plate, to mate with projections extending from a spacer body. A plurality of teeth project from at least one of the upper or lower surfaces of the spacer body, and a chamber is formed through the spacer body to enable bone fusion between the vertebrae. The combined plate and spacer may be inserted to lie completely within the intervertebral space, or a portion of the plate may overlie a vertebral body.

Abstract: The disclosure provides a circuit structure and method to provide self-aligned contacts in a zero-via conductor layer. The structure may include a device layer including a first contact to a first source/drain region, and a second contact to a second source/drain region, the first and second source/drain regions being separated by a transistor gate. A zero-via layer of the circuit structure may include: a first via conductor positioned on the first contact and self-aligned with an overlying metal level in a first direction; and a second via conductor positioned on the second contact and self-aligned with the overlying metal level in a second direction, the second direction being orthogonal to the first direction.

Abstract: The present invention generally is directed toward a spinal fixation system whereby a coupling element allows the physician to selectively lock or unlock either the connection between the coupling element and a fastener, such as to allow for repositioning of the coupling element, or the connection between the coupling element and an elongate rod. The locking or unlocking of these connections may be made independently and as desired by the physician.

Abstract: Disclosed is a reference circuit having an even number m of groups of m parallel-connected magnetic tunnel junctions (MTJs). The MTJs in half of the groups are programmed to have parallel resistances (RP) and the MTJs in the other half are programmed to have anti-parallel resistances (RAP). Switches connect the groups in series, creating a series-parallel resistor network. The total resistance (RT) of the network has low variability and is essentially equal to half the sum of a nominal RP plus a nominal RAP and can be employed as a reference resistance (RREF). Under specific biasing conditions the series-parallel resistor network can generate a low variability reference parameter (XREF) that is dependent on this RREF. Also disclosed are an integrated circuit (IC) that includes the reference circuit and a magnetic random access memory (MRAM) structure, which uses XREF to determine stored data values in MRAM cells and associated methods.

Abstract: A joint spacer therapeutically maintains separation of bones of a joint. A carriage is slideably retained within the frame and has at least one ramped surface. An actuator screw is threadably engaged with the frame, and rotatably connected to the carriage, to cause the carriage to slideably move within the frame when the actuator screw is rotated. First and second endplates engage the bones of the joint, and each has at least one ramped surface that is mateable with the ramped surface of the carriage, whereby when the carriage is slideably moved by rotation of the actuator screw, the endplates ramped surface slides against the carriage ramped surface to cause the endplates to move along an axis transverse to the longitudinal axis of the frame, to increase the height of the spacer. Piercing elements are connected to the carriage to pierce bone of the joint when the carriage is moved.

Abstract: The disclosure provides a circuit structure and method to provide self-aligned contacts in a zero-via conductor layer. The structure may include a device layer including a first contact to a first source/drain region, and a second contact to a second source/drain region, the first and second source/drain regions being separated by a transistor gate. A zero-via layer of the circuit structure may include: a first via conductor positioned on the first contact and self-aligned with an overlying metal level in a first direction; and a second via conductor positioned on the second contact and self-aligned with the overlying metal level in a second direction, the second direction being orthogonal to the first direction.

Abstract: The disclosure provides a circuit structure for storage and retrieval of data, and related methods. The circuit structure may include drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line. A first resistive memory element coupled between the source terminal of the drive transistor and a first bit line may be in a first memory state. A second resistive memory element coupled between the drain terminal of the drive transistor and a second bit line may be in a second memory state opposite the first memory state. The structure may also include a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line.

Abstract: The present disclosure generally relates to semiconductor structures and, more particularly, to twisted wordline structures and methods of manufacture. The memory array structure includes: a plurality of bitcells comprising memory elements and access transistors; a plurality of bitlines and wordlines which interconnect the bitcells; a plurality of dummy bitcells which intersect with the bitlines and wordlines; and a plurality of twisted wordline strap cells which twist wordlines in the dummy bitcells and connect a higher metal layer in the bitcells to a gate structure of the access transistor.

Abstract: The disclosure provides a circuit structure for storage and retrieval of data, and related methods. The circuit structure may include drive transistor having a source terminal, a drain terminal, and a gate terminal coupled to a word line. A first resistive memory element coupled between the source terminal of the drive transistor and a first bit line may be in a first memory state. A second resistive memory element coupled between the drain terminal of the drive transistor and a second bit line may be in a second memory state opposite the first memory state. The structure may also include a read transistor having a source terminal coupled to the drain terminal of the drive transistor, a drain terminal coupled to ground, and a gate terminal coupled to a select line.

Abstract: One illustrative device includes an array of memory cells including a first row of memory cells and a second row of memory cells adjacent the first row, a first gate structure extending along the first row, a second gate structure extending along the second row, a first wordline positioned in a first layer above the array and contacting the first gate structure, and a second wordline positioned in a second layer above the first layer and contacting the second gate structure, wherein the second wordline vertically overlaps the first wordline.

Abstract: The present invention relates generally to a prosthetic spinal disc for replacing a damaged disc between two vertebrae of a spine and methods for inserting said discs. The intervertebral prosthetic discs are provided with connections for facilitating implantation and removal and features which enhance primary and secondary stability over time.