Abstract: One illustrative device disclosed herein includes a first pull-up transistor positioned in a first P-type nano-sheet and a first pull-down transistor and a first pass gate transistor positioned in a first N-type nano-sheet. The device further includes a second pull-up transistor positioned in a second P-type nano-sheet and a second pull-down transistor and a second pass gate transistor positioned in a second N-type nano-sheet. The device further includes a read pull-down transistor and a read pass gate transistor positioned in a third N-type nano-sheet. The device also includes a first shared gate structure positioned adjacent the first pull-up transistor and the first pull-down transistor and a second shared gate structure positioned adjacent the second pull-up transistor, the second pull-down transistor and the read pull-down transistor.

Abstract: One illustrative integrated circuit (IC) product disclosed herein includes a first conductive source/drain contact structure of a first transistor with an insulating source/drain cap positioned above at least a portion of an upper surface of the first conductive source/drain contact structure and a gate-to-source/drain (GSD) contact structure that is conductively coupled to the first conductive source/drain contact structure and a first gate structure of a second transistor. In this example, the product also includes a gate contact structure that is conductively coupled to a second gate structure of a third transistor, wherein an upper surface of each of the GSD contact structure and the gate contact structure is positioned at a first level that is at a level that is above a level of an upper surface of the insulating source/drain cap.

Abstract: Structures for a non-volatile memory and methods for fabricating such structures. An active array region of a memory structure includes a plurality of active bitcells and a wordline. Dummy bitcells of the memory structure are arranged in a column within the active array region. An interconnect structure includes a metallization level having a wordline strap that extends across the active array region and that is arranged over the active array region.

Abstract: Structures for a non-volatile memory and methods for fabricating such structures. An active array region of a memory structure includes a plurality of active bitcells and a wordline. Dummy bitcells of the memory structure are arranged in a column within the active array region. An interconnect structure includes a metallization level having a wordline strap that extends across the active array region and that is arranged over the active array region.

Abstract: A thumb grip cover for an analog controller stick comprised of (a) a screw having (i) a head and (ii) a threaded shank, and (iii) a tip (b) a hardened body comprised of (i) a top surface having a center hole (ii) a bottom surface with a cut-out, preferably a wedge or channel, that ends at or close to the midpoint of the bottom surface (iii) sidewalls that connect the top surface and bottom surface and have an opening dimensioned to receive an uppermost portion of an analog controller stick, comprised of (xx) a hat (i.e., top) and (yy) a shaft wherein the uppermost portion of the analog controller stick is comprised of (xx) a hat and (yy) a shaft.

Abstract: A resilient core is positioned between bony projections which are offset from a principal load bearing region of a spinal joint. Shaped projections extend from the core, and engage the bony projections by conforming to anatomical landmarks, and may be fastened to the bony projections. During flexion of the joint, the core absorbs some of the force of compression, and limits an extent to which the joint may compress. If the shaped projections are connected to the bony projections, extension of the joint is inhibited by the projections and the core, limiting the extent to which the joint may be distracted. In this manner, healing is fostered, and a weakened or damaged joint is protected from excessive movement.

Abstract: A device is disclosed including a first resistive storage element, a first access transistor having a first terminal coupled to the first resistive storage element at a first node, a second resistive storage element, a second access transistor having a first terminal coupled to the second resistive storage element at a second node, and a write assist transistor having a first terminal coupled to the first node and a second terminal coupled to the second node.

Abstract: Systems, components, apparatuses and methodologies of the present invention are directed to techniques that ensure that all deck-to-wall, roof-to-wall and other constructions properly protect the home from the environment, particularly along the wetter coastal regions by forming a layered, waterproof seal of metal, plastic and bitumen. A modularized system of components, that overlap each other either over and or under to create a system that meets the design criteria of critical flashing components, each with waterproofing capability either built-in or applied onsite in use, are employed to cover critical building areas prone to water infiltration and damage.

Abstract: One illustrative method disclosed includes, among other things, selectively forming a gate-to-source/drain (GSD) contact opening and a CB gate contact opening in at least one layer of insulating material and forming an initial gate-to-source/drain (GSD) contact structure and an initial CB gate contact structure in their respective openings, wherein an upper surface of each of the GSD contact structure and the CB gate contact structure is positioned at a first level, and performing a recess etching process on the initial GSD contact structure and the initial CB gate contact structure to form a recessed GSD contact structure and a recessed CB gate contact structure, wherein a recessed upper surface of each of these recessed contact structures is positioned at a second level that is below the first level.

Abstract: Structures for a static random access memory (SRAM) bitcell and methods for forming a SRAM bitcell. The SRAM includes a storage element with a first pull-up (PU) vertical-transport field-effect transistor (VTFET) having a first bottom source/drain region and a fin projecting from the first bottom source/drain region, and a second pull-up (PU) VTFET with a second bottom source/drain region and a fin projecting from the second bottom source/drain region. The fin of the first PU VTFET is arranged over a first active region in which the first bottom source/drain region is centrally arranged, and the fin of the second PU VTFET is arranged over a second active region in which the second bottom source/drain region is centrally arranged. The second source/drain region is aligned with the first bottom source/drain region. A read port may be connected with the storage element, and may also be formed using VTFETs.

Abstract: Disclosed are structures with a complementary field effect transistor (CFET) and a buried metal interconnect that electrically connects a source/drain region of a lower-level transistor of the CFET with another device. The structure can include a memory cell with first and second CFETs, where each CFET includes a pull-up transistor stacked on and having a common gate with a pull-down transistor and each pull-down transistor has a common source/drain region with a pass-gate transistor. The metal interconnect connects a lower-level source/drain region of the first CFET (i.e., the common source/drain region of first pass-gate and pull-up transistors) to the common gate of the second CFET (i.e., to the common gate of second pull-down and pull-up transistors). Formation methods include forming an interconnect placeholder during lower-level source/drain region formation.

Abstract: Structures for a non-volatile memory and methods for forming and using such structures. A bitcell of the non-volatile memory includes a nonvolatile memory element and a field-effect transistor having a drain region coupled with the nonvolatile memory element, a source region, and a gate electrode. A word line is coupled with the gate electrode of the field-effect transistor, a bit line is coupled with the nonvolatile memory element, and a source line is coupled with the source region of the field-effect transistor. A power supply is configured to supply a negative bias voltage to the bit line in order to provide a first state for writing data to the nonvolatile memory element or to supply the negative bias voltage to the source line in order to provide a second state for writing data to the nonvolatile memory element.

Abstract: A resilient core is positioned between bony projections which are offset from a principal load bearing region of a spinal joint. Shaped projections extend from the core, and engage the bony projections by conforming to anatomical landmarks, and may be fastened to the bony projections. During flexion of the joint, the core absorbs some of the force of compression, and limits an extent to which the joint may compress. If the shaped projections are connected to the bony projections, extension of the joint is inhibited by the projections and the core, limiting the extent to which the joint may be distracted. In this manner, healing is fostered, and a weakened or damaged joint is protected from excessive movement.

Abstract: One illustrative device disclosed herein includes a first pull-up transistor positioned in a first P-type nano-sheet and a first pull-down transistor and a first pass gate transistor positioned in a first N-type nano-sheet. The device further includes a second pull-up transistor positioned in a second P-type nano-sheet and a second pull-down transistor and a second pass gate transistor positioned in a second N-type nano-sheet. The device further inlcudes a read pull-down transistor and a read pass gate transistor positioned in a third N-type nano-sheet. The device also includes a first shared gate structure positioned adjacent the first pull-up transistor and the first pull-down transistor and a second shared gate structure positioned adjacent the second pull-up transistor, the second pull-down transistor and the read pull-down transistor.

Abstract: An intervertebral prosthetic implant having a first endplate having a first surface configured to substantially engage with a first vertebral body and a second surface having an extension with a concave contact surface, the concave contact surface being spaced apart from the second surface. A second endplate is provided with a first surface configured to substantially engage with a second vertebral body and a second surface comprising a convex contact surface, and the second endplate having a securing element positioned along and above the second surface defining a first and second window on opposing sides of the second surface. The securing element extends along the width and length of the lower endplate and configured with an access hole. An extension portion extends from the first surface of the first endplate through the access hole of the securing element and contacts the second surface of the second endplate.

Abstract: Embodiments of the present disclosure relate to apparatus and methods for forming films having uniformity of thickness on substrates. Embodiments of the present disclosure may be used to measure thickness or other properties of films being deposited on a substrate without knowing beforehand the surface properties of the substrate. Embodiments of the present disclosure may be used to measure thickness or other properties of a plurality of layers being formed. For example, embodiments of the present disclosure may be used in measuring thickness of vertical memory stacks.

Abstract: A magneto-resistive memory (MRM) structure includes a source line and a first transistor that includes a source region and a drain region. The source line is electrically connected to the source region of the first transistor. The MRM structure further includes an MRM cell that includes an MRM transistor electrically in series with an MRM magnetic tunnel junction (MTJ). The MRM transistor is electrically connected to the drain region of the first transistor such that the MRM cell is electrically in series with the first transistor. Still further, the MRM structure further includes a voltage amplifier electrically connected to a mid-point node of the first transistor and the MRM transistor, a sense-amplifier electrically connected to the voltage amplifier, and a bit line electrically connected to the MRM MTJ of the MRM cell.

Abstract: Integrated circuits, memory arrays and methods for operating integrated circuit devices are provided. In an embodiment, an integrated circuit includes a selected column of bit cells, wherein each bit cell in the selected column is coupled to a source line and coupled to a bit line. Further, the integrated circuit includes a first column of bit cells laterally adjacent the selected column, wherein each bit cell in the first column is coupled to the source line. Also, the integrated circuit includes a second column of bit cells laterally adjacent the selected column, wherein each bit cell in the second column is coupled to the bit line.

Abstract: A method includes forming a first gate structure above a first region of a semiconducting substrate. A first sidewall spacer is formed adjacent the first gate structure. The first gate structure and the first sidewall spacer are recessed to define a first gate contact cavity. A second sidewall spacer is formed in the first gate contact cavity. A first conductive gate contact is formed in the first gate contact cavity. The second sidewall spacer is removed to define a first spacer cavity. A conductive material is formed in the first spacer cavity to form a first conductive spacer contacting the first conductive gate contact.

Abstract: The present invention generally is directed toward a spinal fixation system whereby a coupling element allows the physician to selectively lock or unlock either the connection between the coupling element and a fastener, such as to allow for repositioning of the coupling element, or the connection between the coupling element and an elongate rod. The locking or unlocking of these connections may be made independently and as desired by the physician.