Patents by Inventor C. Yu

C. Yu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 7030001
    Abstract: One embodiment forms a gate dielectric layer over a substrate and then selectively deposits a first metal layer over portions of the gate dielectric layer in which a first device type will be formed. A second metal layer, different from the first metal layer, is formed over exposed portions of the gate dielectric layer in which a second device type will be formed. Each of the first and second device types will have different work functions because each will include a different metal in direct contact with the gate dielectric. In one embodiment, the selective deposition of the first metal layer is performed by ALD and with the use of an inhibitor layer which is selectively formed over the gate dielectric layer such that the first metal layer may be selectively deposited on only those portions of the gate dielectric layer which are not covered by the inhibitor layer.
    Type: Grant
    Filed: April 19, 2004
    Date of Patent: April 18, 2006
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Olubunmi O. Adetutu, Lynne M. Michaelson, Kathleen C. Yu, Robert E. Jones, Jr.
  • Patent number: 7005222
    Abstract: An imaging member having a charge transport layer with multiple regions is provided. The charge transport layer includes a plurality of charge transport layers coated from solutions of similar or different compositions or concentrations, wherein at least the top or uppermost transport layer comprises a lower concentration of charge transport compound than the first (bottom) charge transport layer. The charge transport compound included in the first (bottom) charge transport layer may either be of the same or different compounds from that included in the top or additional charge transport layer(s). The charge transport compound present in each layer may be dissolved or molecularly dispersed in an electrically inactive polymer material to form a solid solution. In such a construction, the resulting charge transport layer exhibits enhanced cracking suppression, improves wear resistance, provides excellent imaging member electrical performance, and delivers improved print quality.
    Type: Grant
    Filed: December 16, 2003
    Date of Patent: February 28, 2006
    Assignee: Xerox Corporation
    Inventors: Anthony M. Horgan, Satchidanand Mishra, Robert C. Yu, Richard L. Post, Edward F. Grabowski, Kathleen M. Carmichael, John R. Lambie
  • Patent number: 6957385
    Abstract: A worldwide number format for use with a spreadsheet program module is disclosed. The worldwide number format includes a locale specifier comprising a number shape, a calendar type and a locale identification (LCID). The worldwide number format also includes a base number format and a value. The LCID is used to categorize different parts of the world. Primarily, the LCID categorizes different parts of the world by language such as English, German, French, Thai, Arabic, etc. The LCID is used to determine what language to display month names, month abbreviations, weekday names, weekday abbreviations, time designations such as AM/PM, etc. The calendar type supports both Gregorian and non-Gregorian calendars. Calendar type is a value to indicate which calendar should be used to calculate the date from the value. The number shape is a value that indicates what shape in which to represent the number.
    Type: Grant
    Filed: January 5, 2001
    Date of Patent: October 18, 2005
    Assignee: Microsoft Corporation
    Inventors: Marise Chan, Barry C. McCord, Kenneth E. Schmidt, James Sukhabut, Christopher C. Yu
  • Patent number: 6953828
    Abstract: Blends of very low density polyethylene produced using metallocene catalysts (mVLDPE) and polypropylene are disclosed. The polymer blends include a metallocene-catalyzed VLDPE polymer having a density of less than 0.916 g/cm3, the mVLDPE polymer preferably being linear and without long chain branching, a polypropylene homopolymer, random copolymer, or impact copolymer, and optionally flame retardant additives. The polymer blends are particularly suitable in membrane applications where increased tear resistance and tensile strength are desirable, such as in roof membranes, geomembranes, and pond liners.
    Type: Grant
    Filed: September 3, 2002
    Date of Patent: October 11, 2005
    Assignee: ExxonMobil Chemical Patents, Inc.
    Inventors: Raja N. Dharmarajan, Thomas C. Yu
  • Patent number: 6930222
    Abstract: The present invention provides a process for making an in vivo model of human leukemia. The process includes the steps of: pre-conditioning an immunodeficient rodent by administering to the rodent a sub-lethal dose of irradiation and injecting the rodent with an effective pre-conditioning amount of human fetal cord blood mononuclear cells; maintaining the rodent for from about 5 to 10 days; and injecting the rodent with an effective engrafting amount of primary human leukemia cells. An in vivo and in vitro model of human leukemia are also provided.
    Type: Grant
    Filed: August 22, 2001
    Date of Patent: August 16, 2005
    Assignee: The Scripps Research Institute
    Inventor: John C. Yu
  • Patent number: 6922987
    Abstract: The present invention provides for a system and process for enhancing internal combustion engine aftertreatment applications by superheated fuel injection. The system includes a fuel supply upstream of a fuel injector of an aftertreatment application. The system also includes a heater for heating the fuel in the fuel supply. A temperature controller can be used to maintain the heated fuel in a liquid form. When liquid fuel in the pressurized fuel supply is heated, then upon exiting the injector the pressure of the fuel drops rapidly, resulting in atomization of the liquid. The vaporized fuel thereby produced is comprised of extremely small droplets and is elevated in temperature, which reduces the possibility of condensation on internal surfaces of the aftertreatment system. This fine droplet size and resistance to condensation enhances the NOx conversion efficiency of adsorbers. Problems related to premature aging of catalysts and fuel penalties can also be reduced.
    Type: Grant
    Filed: February 12, 2003
    Date of Patent: August 2, 2005
    Assignee: Fleetguard, Inc.
    Inventors: Rahul Mital, Scott Cole, Robert C. Yu, Mike Nagel
  • Patent number: 6921961
    Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
    Type: Grant
    Filed: September 22, 2004
    Date of Patent: July 26, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hector Sanchez, Michael A. Mendicino, Byoung W. Min, Kathleen C. Yu
  • Patent number: 6887552
    Abstract: A headliner assembly, for use with a vehicle having a roof, includes a headliner body that is positionable proximate the roof, and a support frame attached to the headliner body. The support frame cooperates with the headliner body to provide a sufficient structural characteristic such that the headliner assembly is self-supporting.
    Type: Grant
    Filed: December 19, 2002
    Date of Patent: May 3, 2005
    Assignee: Lear Corporation
    Inventors: Michael C. Dykman, Carter S. Cannon, Lorraine C. Yu, Gordon L. Ebbitt, Michelle W. Jones
  • Patent number: 6885978
    Abstract: An auto-determination technique detects whether a DTE or DCE is connected to an RS232 port. The port is then automatically configured to interface with the connected equipment.
    Type: Grant
    Filed: March 19, 2003
    Date of Patent: April 26, 2005
    Assignee: Cisco Technology, Inc.
    Inventors: Steve Chu, Jicheng Ye, George C. Yu
  • Patent number: 6884729
    Abstract: Methods for manufacturing substrates with difficult to polish features using reverse mask etching and chemical mechanical planarization techniques.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: April 26, 2005
    Assignee: Cabot Microelectronics Corporation
    Inventors: Jui-Kun Lee, Chris C. Yu, David G. Mikolas
  • Publication number: 20050048044
    Abstract: The present invention relates to altering the physical and/or chemical properties of at least part of at least one tissue in the eye. In a specific embodiment, it relates to the treatment of any eye disorder, although in particular embodiments the individual has a thickened Bruch's membrane. An activating energy source is utilized to effect a controlled diffusion enhancement and/or degradation of Bruch's membrane that enables improved diffusional transport between the choroid and retina. The individual is administered an inactivated diffusion-enhancing molecule that becomes associated with the membrane, which is then precisely exposed to an activating energy source, such as light or ultrasound.
    Type: Application
    Filed: July 1, 2003
    Publication date: March 3, 2005
    Applicants: THE REGENTS OF THE UNIVERSITY OF CALIFORNIA, THE CALIFORNIA INSTITUTE OF TECHNOLOGY
    Inventors: Daniel Schwartz, Scott Fraser, Robert Grubbs, Justin Gallivan, C. Yu
  • Patent number: 6853474
    Abstract: A process for fabricating micro-acousto-optic modulators using microelectronics fabrication technology. First, a set of trenches is etched into a substrate. Then, a transducer material is deposited into these trenches, followed by removal of any transducer material located above the surface of the substrate. Next, a second set of trenches is etched on both sides of the transducer material, between the transducer material and the substrate. Then, an electrode material is deposited into the second set of trenches. Finally, any electrode material located above the surface of the substrate is removed such that the surface of the substrate is co-planar with the electrode and transducer materials.
    Type: Grant
    Filed: April 4, 2002
    Date of Patent: February 8, 2005
    Assignee: Cabot Microelectronics Corporation
    Inventors: Chris C. Yu, Vlasta Brusic
  • Patent number: 6838354
    Abstract: Dummy features (64, 65, 48a, 48b) are formed within an interlevel dielectric layer (36). Passivation layers (32 and 54) are formed by electroless deposition to protect the underlying conductive regions (44, 48a, 48b and 30) from being penetrated from the air gaps (74). In addition, the passivation layers (32 and 54) overhang the underlying conductive regions (44, 48a, 48b and 30), thereby defining dummy features (65a, 65b and 67) adjacent the conductive regions (48a, 44 and 48b). The passivation layers (32 and 54) can be formed without additional patterning steps and help minimize misaligned vias from puncturing air gaps.
    Type: Grant
    Filed: December 20, 2002
    Date of Patent: January 4, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Cindy K. Goldberg, Stanley Michael Filipiak, John C. Flake, Yeong-Jyh T. Lii, Bradley P. Smith, Yuri E. Solomentsev, Terry G. Sparks, Kirk J. Strozewski, Kathleen C. Yu
  • Patent number: 6838332
    Abstract: A semiconductor (10) has an active device, such as a transistor, with a directly underlying passive device, such as a capacitor (75, 77, 79), that are connected by a via or conductive region (52) and interconnect (68, 99). The via or conductive region (52) contacts a bottom surface of a diffusion or source region (22) of the transistor and contacts a first (75) of the capacitor electrodes. A laterally positioned vertical via (32, 54, 68) and interconnect (99) contacts a second (79) of the capacitor electrodes. A metal interconnect or conductive material (68) may be used as a power plane that saves circuit area by implementing the power plane underneath the transistor rather than adjacent the transistor.
    Type: Grant
    Filed: August 15, 2003
    Date of Patent: January 4, 2005
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Hector Sanchez, Michael A. Mendicino, Byoung W. Min, Kathleen C. Yu
  • Patent number: 6832493
    Abstract: The present invention relates to a method for forming an optical device. The method includes providing a glass aggregate. Typically, the glass aggregate is a mixture of fine glass soot particles and coarser ground or milled glass powder. The glass particles are mixed with a liquid to form a slurry which is cast in a mold to form a porous pre-form. Subsequently, the porous pre-form is consolidated into a glass object by heating the pre-form at a relatively high temperature. The method of the present invention produces optical components having substantially no striae. As a result, scattering is substantially reduced when EUV light is reflected from a component produced from the optical blank.
    Type: Grant
    Filed: February 27, 2002
    Date of Patent: December 21, 2004
    Assignee: Corning Incorporated
    Inventors: Bradley F. Bowden, Kenneth E. Hrdina, John F. Wight, Jr., Chunzhe C. Yu
  • Publication number: 20040249106
    Abstract: The present invention relates to isocyanate functional prepolymers, aqueous polyurethane dispersions produced from the prepolymers and various uses of such dispersions.
    Type: Application
    Filed: June 3, 2003
    Publication date: December 9, 2004
    Inventors: Lyubov K. Gindin, Richard R. Roesler, Poli C. Yu, Joseph R. Kleer, Thomas Muenzmay, Yuliya Berezkin, Mary A. Crisci
  • Patent number: 6820414
    Abstract: The present invention provides for adsorber catalysts arranged in parallel. The exhaust flow from the engine is divided in a predetermined ratio between the two catalysts during lean operation (e.g. 50-50). At a predetermined regeneration time (for example, when the adsorber catalyst is 20% full), the exhaust gas flow is reduced through the parallel leg that is to be regenerated (e.g. 20-80). A quantity of hydrocarbon is injected into the reduced-flow leg in order to make the mixture rich. Once the leg has been regenerated, the flow distribution between the parallel legs is reversed, and the other catalyst leg is regenerated while the other side (which is now clean) receives the majority of the exhaust flow. Once both catalyst legs have been regenerated, the exhaust flow is adjusted back to normal (e.g. 50-50) until the catalysts are again ready for regeneration and reduction. A catalytic soot filter is positioned downstream from the adsorber.
    Type: Grant
    Filed: July 11, 2002
    Date of Patent: November 23, 2004
    Assignee: Fleetguard, Inc.
    Inventors: Bradlee J. Stroia, Robert C. Yu, Rahul Mital, Michael J. Cunningham
  • Patent number: 6815820
    Abstract: A conductive line varies in thickness to assist in overcoming RC delays and noise coupling. By varying line thickness, variation in conductor width is avoided if necessary to maintain a specified minimum pitch between conductors while maintaining predetermined desired RC parameters and noise characteristics of the conductive line. Conductor depth variation is achieved by etching a dielectric layer to different thicknesses. A subsequent conductive fill over the dielectric layer and in the differing thicknesses results in a conductive line that varies in thickness. Different conductive line thicknesses available at a particular metal level can additionally be used for semiconductor structures other than a signal or a power supply conductive line, such as a contact, a via or an electrode of a device. The thickness analysis required to determine how interconnect thickness is varied in order to meet a desired design criteria may be automated and provided as a CAD tool.
    Type: Grant
    Filed: May 9, 2002
    Date of Patent: November 9, 2004
    Assignee: Freescale Semiconductor, Inc.
    Inventors: Kathleen C. Yu, Kirk J. Strozewski, Janos Farkas, Hector Sanchez, Yeong-Jyh T. Lii
  • Publication number: 20040210026
    Abstract: Isocyanate-functional polyurethane prepolymers and aqueous dispersions therefrom which are useful for the production of flat materials having excellent resistance to alcoholic solvents are described.
    Type: Application
    Filed: October 2, 2003
    Publication date: October 21, 2004
    Inventors: Eduard Mayer, Thomas Muenzmay, Yuliya Berezkin, Poli C. Yu, Richard R. Roesler, Mary A. Crisci
  • Publication number: 20040204547
    Abstract: Blends of very low density polyethylene produced using metallocene catalysts (mVLDPE) and polypropylene are disclosed. The polymer blends include a metallocene-catalyzed VLDPE polymer having a density of less than 0.916 g/cm3, the mVLDPE polymer preferably being linear and without long chain branching, a polypropylene homopolymer, random copolymer, or impact copolymer, and optionally flame retardant additives. The polymer blends are particularly suitable in membrane applications where increased tear resistance and tensile strength are desirable, such as in roof membranes, geomembranes, and pond liners.
    Type: Application
    Filed: March 11, 2004
    Publication date: October 14, 2004
    Inventors: Raja N. Dharmarajan, Thomas C. Yu