Abstract: The present invention provides a process for making an in vivo model of human leukemia. The process includes the steps of: pre-conditioning an immunodeficient rodent by administering to the rodent a sub-lethal dose of irradiation and injecting the rodent with an effective pre-conditioning amount of human fetal cord blood mononuclear cells; maintaining the rodent for from about 5 to 10 days; and injecting the rodent with an effective engrafting amount of primary human leukemia cells. An in vivo and in vitro model of human leukemia are also provided.

Abstract: A pipelined analog to digital converter for converting an analog signal to a sequence of digital words, each such word representing a value of the analog signal at a time in a succession of times. The converter includes a sequence of analog to digital converter stages, each such stage generating at least one bit for each such word. A first such stage in the sequence receives the analog signal, and each such stage subsequent to the first stage receives a residue signal from a previous stage in the sequence. Each such stage includes an analog to digital unit that senses a sample of the analog signal and provides one or more bits representing a value of the sample. In at least one of the stages the analog to digital unit comprises a &Sgr;-&Dgr; converter.

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.

Abstract: A method of fabricating a semiconductor device is described in which an insulation layer is formed over the gate electrode and the substrate. This insulation layer is anisotropically etched away except for a portion surrounding the sidewall of the gate electrode to form a spacer. The tip of the spacer is at the same height as the upper surface of the liner layer and is lower than the upper surface of the gate electrode, therefore, resulting in an increase of the exposed area of the gate electrode surface.

Abstract: A multi-stage analog-to-digital converter (“ADC”) for converting an analog input signal to a series of digital values, each having a first plurality of bits, representing the voltage levels of the analog input signal at a corresponding series of sample times. The ADC includes a plurality of analog-to-digital converter stages connected serially in pipeline configuration. One or more of such stages includes an analog-to-digital subconverter, providing a second plurality of bits of the digital value, where the second plurality is smaller than the first plurality, the analog-to-digital subconverter including a plurality of analog-to-digital subconverter substages connected serially in pipeline configuration. Each such subconverter substages provides one or more bits of the second plurality of bits.

Abstract: The invention describes a method for fabricating an inter-layer dielectric layer. In this method, a plurality of first polysilicon lines, a first inter-layer dielectric layer, and a plurality of second polysilicon lines are formed in sequence on the substrate. A second inter-layer dielectric layer is formed between the plurality of second polysilicon lines and entirely covers the plurality of second polysilicon lines. Afterwards, a spin-on glass layer is formed on the second inter-layer dielectric layer, and then, while using the upper surfaces of the second polysilicon lines as etch end points, the spin-on glass layer and the second inter-layer dielectric layer are etched back to entirely remove the spin-on glass layer and partially remove the second inter-layer dielectric layer over the second polysilicon lines. Subsequently, a cover layer is formed to cover the second polysilicon lines and the remainder of the inter-layer dielectric layer. Finally, an oxide layer is formed to cover the resulting structure.

Abstract: A method and apparatus of correcting for saturation in a current transformer, which outputs a current measurement, is provided. A switching algorithm receives a value of the current measurement from the current transformer and determines within which of three ranges the value falls. If the value falls in a first range, the current measurement is provided to a protective device such as a relay. If the value falls in a second range, the current measurement is provided to an artificial neural network that produces an output that accounts for saturation of the current transformer. If the value falls in a third range, the current measurement is provided to another artificial neural network that produces an output that accounts for saturation of the current transformer.

Abstract: A unified program method and circuitry for performing concurrently a programming and verifying operation in an array of Flash EEPROM memory cells is provided. Each of the memory cells includes a floating gate array core transistor. A single bandgap voltage is provided which corresponds to a predetermined amount of drain current at which programming is to be terminated. A program voltage is selectively connected to at least one of the columns of array bit lines containing the array core transistor which is to be programmed. A control gate bias voltage corresponding to a programmable memory state is selectively connected to the gate of the array core transistor. A core cell current flowing through the array core transistor and the predetermined amount of drain current is compared. The program voltage is disconnected so as to terminate automatically programming of the array core transistor when the core cell current falls below the predetermined amount of drain current.

Abstract: A method for shuffling capacitors from period to sample period in a stage of a multi-stage analog to digital converter (“ADC”). The ADC stage includes a plurality of capacitors usable for storage of charge during a sample phase and for providing during an amplification phase, in conjunction with an amplifier, an output signal having a voltage representing the difference between the digital output voltage level for the stage and the analog input voltage level for the stage. The method includes the following steps. First, the input is provided to the plurality of capacitors during the sample phase to capture and hold the first analog voltage level at a first time in the sample phase.

Abstract: An analog-to-digital converter system 10 is provided that comprises an analog-to-digital converter pipeline 12 coupled to a memory system 14 and a calibration system 16. An arithmetic logic unit 18 receives a raw output from the analog-to-digital converter system 12 and calibration quantities from the calibration system 16 to generate a calibrated output. The calibration system 16 is able to iteratively generate multiple order calibration values that can be used to eliminate capacitor mismatch errors. The techniques described are equally applicable to analog-to-digital converter architectures which resolve multiple bits per stage of the analog-to-digital converter system.

Abstract: A user transparent self-calibration technique for an analog to digital converter is described. The technique can correct for capacitor mismatch error with minimal additional power consumption. This is done by generating a calibration signal, one for each capacitor whose calibration is desired. The signal is interleaved with the input signal, and digitized by alternating with the input signal digitization using capacitor arrays.

Abstract: An output noise control circuit with significantly reduced power/ground bounce characteristics when multiple outputs thereof are being simultaneously switched is provided. The output noise control circuit includes a plurality of output buffers each being formed of an output driver stage, a first pre-driver stage, and a second pre-driver stage. Each of the output driver stages includes a pull-up drive transistor and a pull-down drive transistor. Each of the first pre-driver stages includes a first inverter, and each of said second pre-driver stages includes a second inverter. A shared pull-up resistor has its one end coupled to each of the first pre-driver stage inverters and its other end connected to a ground potential node. A shared pull-down resistor has its one end coupled to each of the second pre-driver stage inverters and its other end connected to a power supply potential node.

Abstract: A unified erase method used in an array of flash EEPROM memory cells arranged in a plurality of sectors for performing either a single-sector, multiple-sector, or all-sector erasing operation with a reduced amount of total erase time and a uniform VT distribution as good as that of a single-sector erase operation is provided. An erase-verify operation is performed sequentially on the plurality of sectors from a first sector to a last sector beginning with a first address of each sector if its corresponding erase-on signal is not turned OFF. The current address of each sector is stored at a point where the erase-verify operation failed. An erase pulse is applied only to all sectors simultaneously that have not passed the erase-verify operation. The erase-verify operation is then repeated beginning at the current address stored. The erasing operation is terminated when the erase-on signal has been turned OFF in all sectors in the plurality of sectors.

Abstract: An analog-to-digital converter system 10 is provided that comprises two separate banks of capacitors that are configured with a single operational amplifier 30 for each stage 29 within the system 10. The banks of capacitors are used in an interleaved fashion to simultaneously digitize analog input voltages and sample a reference voltage V.sub.REF to enable the digitization of a gain error associated with the operation of amplifier 30. This gain error can be combined with the raw digital output of the converter using an arithmetic logic unit 18 to result in a calibrated output for the system 10.

Abstract: A method for fabricating an electrochromic device having organic polymer substrates is described. Each substrate has a surface coated with an organic polymer primer coating onto which is deposited an electroconductive metal oxide film. An electrochromic material is deposited on one electroconductive film and a complementary electrochromic material is deposited on the other electroconductive film. The resultant two substrates are aligned with the electrochromic materials facing one another. A preformed sheet of an ion-conducting polymer is disposed between those electrochromic layers and the resulting sandwich autoclaved.

Abstract: Various modified carbon products are disclosed which can form a part of a polymeric product containing the modified carbon product and a polymer. One type of modified carbon product disclosed is a carbon product having attached at least one organic group, monomeric group, or polymeric group. Another type of modified carbon product disclosed is a carbon product having attached a group having the formula: --Ar--CO.sub.2 --R or --(--C.sub.n H.sub.2n --)--CO.sub.2 --R, where R is an organic group, monomeric group, or a polymeric group.

Abstract: The present invention relates to aqueous solutions or dispersions of compounds, which contain 0.5 to 6% by weight of alkoxysilane and/or silanol groups (calculated as Si, MW 28), based on the weight of the compounds containing alkoxysilane groups, and are substantially free from isocyanate groups and chemically incorporated hydrophilic groups, wherein the alkoxysilane groups are initially incorporated by the reaction of a polyisocyanate with an amino compound corresponding to formula I ##STR1## wherein X represents identical or different organic groups which are inert to isocyanate groups below 100.degree. C., provided that at least one of these groups is an alkoxy group,Y represents a linear or branched alkylene group having 1 to 8 carbon atoms andR.sub.1 represents an organic group which is inert to isocyanate groups at a temperature of 100.degree. C. or less.The present invention also relates to coating, adhesive or sealing compositions containing these aqueous compounds as the binder.

Abstract: The present invention relates to aqueous solutions or dispersions of compositions containingA) compounds, which contain 0.5 to 15% by weight of alkoxysilane and/or silanol groups (calculated as Si, MW 28), based on the weight of the compounds containing alkoxysilane groups, and are substantially free from isocyanate groups and chemically incorporated hydrophilic groups, wherein the alkoxysilane groups are initially incorporated by the reaction of a polyisocyanate with an amino compound corresponding to formula I ##STR1## wherein X represents identical or different organic groups which are inert to isocyanate groups below 100.degree. C., provided that at least one of these groups is an alkoxy group,Y represents a linear or branched alkylene group having 1 to 8 carbon atoms andR.sub.1 represents an organic group which is inert to isocyanate groups at a temperature of 100.degree. C.

Abstract: An exercising dumbbell comprising a tubular body with attached "U" shaped handle for use with two hands. The body contains a D.C. motor which is geared to a stationary central shaft and which may rotate around the shaft to generate strong vibrations. Batteries are contained within the handle and motor speed is varied from zero to maximum by pressure activated switches under each hand. Function switches on the body reverse motor direction, permit one-hand, both-hand or hands-free operation, provide music through an included speaker, and generate an exhilarating train of pulses.

Abstract: In one embodiment of the invention, conductive support structures (112) are formed within an interlevel dielectric layer. The conductive support structures (112) lie within the bond pad region (111) of the integrated circuit and provide support to portions of the interlevel dielectric layer that have a low Young's modulus. The conductive support structures (112) are formed using the same processes that are used to form metal interconnects in the device region (109) of the integrated circuit, but they are not electrically coupled to semiconductor devices that lie within the device region (109). Conductive support structures (114) are also formed within the scribe line region (104) to provide support to the interlevel dielectric layer in this region of the integrated circuit.