Abstract: A thin film transistor (TFT), a manufacturing method, an array substrate, a display panel, and a device is disclosed. The TFT includes a hydrogen-containing buffer layer located on a substrate; an oxide semiconductor layer located on the buffer layer, wherein the oxide semiconductor layer includes a conductor region and a semiconductor region; a source or drain located on the conductor region, and electrically connected to the conductor region; and a gate structure located on the semiconductor region.

Abstract: The disclosure relates to a thin film transistor structure, an array substrate, and a method for manufacturing a thin film transistor structure. The thin-film transistor structure includes a base substrate, a thin film transistor on the base substrate. Wherein the thin film transistor includes an active layer and a source/drain electrode on a side, facing towards the base substrate, of the active layer. Wherein the source/drain electrode has a protrusion protruding from an edge portion of the active layer in a direction parallel to a surface of the base substrate.

Abstract: A metal oxide film and a manufacturing method thereof, a thin film transistor and an array substrate are provided. The manufacturing method of the metal oxide film includes: forming a metal oxide film on a base substrate; and supplying a negative ion to the metal oxide film for a preset time period by performing a anodization method, to convert a portion of metal ions in the metal oxide film into a metal oxide.

Abstract: A method of manufacturing a display substrate includes: providing a base substrate; and forming a base insulating layer, a first conductive layer and an interlayer insulating layer that are sequentially stacked on top of one another at a side of the base substrate. The first conductive layer includes at least one break face, the base insulating layer includes a portion extending outward with respect to each of the at least one break face, and the break face and the corresponding portion extending outward constitute an unevenness portion having a stepped shape. The interlayer insulating layer covers at least the unevenness portion(s). Forming the interlayer insulating layer, includes: forming a first insulating sub-layer and a second insulating sub-layer that are sequentially stacked on top of one another; and forming one of the first insulating sub-layer and the second insulating sub-layer by curing a flowable insulating material.

Abstract: The present disclosure provides a method for preparing an interlayer insulating layer and a method for manufacturing a thin film transistor, and a thin film transistor, belongs to the field of display technology, and can solve the problem of poor resistance to breakdown of the interlayer insulating layer in the related art. The method for preparing an interlayer insulating layer includes the following steps: forming a silicon oxide layer with a first reaction gas and forming a silicon nitride layer with a second reaction gas such that hydrogen content in the silicon nitride layer is less than or equal to hydrogen content in the silicon oxide layer.

Abstract: A display panel includes a substrate; a conductive layer disposed on the substrate; a gate insulating layer disposed on the conductive layer; a gate layer disposed on the gate insulating layer, wherein the gate layer has a thickness larger than a thickness of the conductive layer; a groove extending toward the substrate and punching through the gate layer, orthographic projections of the groove and the conductive layer on the substrate overlapping, and gate layers separated on two sides of the groove being connected to the conductive layer; an interlayer dielectric layer disposed on a side of the gate layer away from the substrate and covering the conductive layer and filling the groove; and an auxiliary electrode layer disposed on the interlayer dielectric layer, wherein the orthographic projections of the auxiliary electrode layer and the gate layer on substrate do not overlap, and the orthographic projections of the auxiliary electrode layer and the groove on the substrate overlap.

Abstract: A pressure sensing unit includes: a first substrate and a second substrate opposite to each other; and at least one vertical thin film transistor disposed between the first substrate and the second substrate. Each vertical thin film transistor includes a first electrode, a semiconductor active layer, a second electrode, at least one insulating support, and a gate electrode sequentially disposed in a direction extending from the first substrate to the second substrate. A first air gap is formed by the presence of the at least one insulating support between the gate electrode and the second electrode of each vertical thin film transistor.

Abstract: Provided is a thin film transistor, including: a conductive light shielding layer; a metal oxide layer arranged on the light shielding layer; a buffer layer, an active layer, a gate insulating layer, a gate electrode, and an interlayer insulating layer arranged in sequence on the metal oxide layer, the interlayer insulating layer and the buffer layer comprising a first via hole and a second via hole for exposing the active layer, and a third via hole for exposing the metal oxide layer, in which a portion of the metal oxide layer exposed through the third via hole is a conductive portion, and other portions are insulative; and a source electrode and a drain electrode arranged on the interlayer insulating layer, in which the source electrode is connected to the active layer through the first via hole, and the drain electrode is connected to the active layer through the second via hole and connected to the conductive portion through the third via hole.

Abstract: The present disclosure provides a pixel defining layer and a preparation material thereof, and a display substrate and a preparation method thereof, and relates to the field of display technologies. The preparation material of the pixel defining layer comprises the following components in mass percentages: 5%-30% of a lyophobic film-forming polymer, 0.5%-1% of lyophilic magnetic nanoparticles, 0.5%-2% of a photoinitiator, 0.1%-1% of a reactive monomer, 0.1%-1% of an additive and the balance of a solvent.

Abstract: A method for manufacturing a thin film transistor includes forming a light shielding layer and a buffer layer covering the light shielding layer on a substrate. The method includes forming an active layer including a peripheral region and a channel region. The method includes forming a gate insulating layer covering the channel region and forming a contact hole exposing the light shielding layer. The method includes forming a source region and a drain region disposed on both sides of the channel region. The method includes forming an electrode layer including a gate electrode, a source electrode and a drain electrode spaced apart one another. The method includes forming a dielectric layer covering the gate electrode, the source electrode, the drain electrode and the buffer layer.

Abstract: There are provided a thin-film transistor and a production method thereof, an array substrate, and a display panel. The method comprises forming an active layer, a gate insulating layer, and a gate electrode on a substrate, wherein conductor conversion treatment is performed on both sides of the homogeneous active material layer to obtain an active layer, and the active layer comprises conductor regions located at both sides and a non-conductor region located at the center, wherein a projection of the gate electrode on the substrate is within a projection of the non-conductor region on the substrate, and the distances from the projection of the gate electrode to projections of the two conductor regions on the substrate are each between 0 micrometer and 1 micrometer.

Abstract: An embodiment of an adaptive video encoder may include technology to determine headset-related information including at least one of focus-related information and motion-related information, and determine one or more video encode parameters based on the headset-related information. Other embodiments are disclosed and claimed.

Abstract: The present disclosure provides a transistor and a manufacturing method thereof, a display substrate and a display device. The transistor includes: a base structure; an active layer on the base structure; and a gate electrode, a source electrode and a drain electrode that are all located on a side of the active layer distal to the base structure. The active layer includes a first region corresponding to an orthographic projection of the gate electrode on the base structure and a second region outside the orthographic projection. A surface of the base structure in contact with the active layer in the first region is not in the same plane as a surface of the base structure in contact with the active layer in the second region. The active layer in the first region has substantially the same thickness as a thickness of the active layer in the second region.

Abstract: A display back plate, a fabricating method for the same, and a display device are provided. The display back plate includes a substrate, a transparent heat conduction layer disposed on the substrate, and an array structure layer disposed on the heat conduction layer. The array structure layer includes a light shielding layer, a first thin film transistor, and a second thin film transistor, where the light shielding layer is disposed between the transparent heat conduction layer and the first thin film transistor.

Abstract: A display panel, a method for manufacturing the display panel, and a display apparatus are provided. The display panel includes a base substrate; a thin film transistor; an OLED structure formed on the thin film transistor including a first and second electrodes arranged opposite to each other and an organic light emitting layer arranged between the first and second electrodes; a light shielding layer arranged between the first electrode and the organic light emitting layer. The light shielding layer includes a first and a second light shielding layers. The first light shielding layer includes a first light shielding portion and a first opening portion corresponding to a pixel area. The second light shielding layer includes a second light shielding portion and a second opening portion corresponding to a pixel area. The second light shielding portion includes a first and second parts.

Abstract: A flexible display panel and a film-like structure are provided according to the present disclosure. The flexible display panel includes a flexible display structure and a film-like structure arranged on at least one side of the flexible display structure. The film-like structure includes: a first flexible layer, a second flexible layer, a filler sealed between the first flexible layer and the second flexible layer, and a heater configured to heat the filler. A hardness of the filler varies with a temperature of the filler.

Abstract: A fabrication method for fabricating a thin-film transistor includes: forming a light shielding layer on a substrate; forming a buffer layer covering the light shielding layer, and forming a semiconductor material layer stacked on a surface of the buffer layer away from the substrate; forming a through hole penetrating through the buffer layer and the semiconductor material layer; patterning the semiconductor material layer to form an active layer covering a partial region of the buffer layer; forming a gate insulator layer on a surface of the active layer away from the substrate and a gate stacked on a surface of the gate insulator layer away from the substrate; forming a source and a drain on the surface of the buffer layer away from the substrate; and forming a dielectric layer covering the gate, the source, the drain, and the buffer layer, and being recessed into the through hole to form a groove.

Abstract: A method for manufacturing a thin film transistor includes forming a light shielding layer and a buffer layer covering the light shielding layer on a substrate. The method includes forming an active layer including a peripheral region and a channel region. The method includes forming a gate insulating layer covering the channel region and forming a contact hole exposing the light shielding layer. The method includes forming a source region and a drain region disposed on both sides of the channel region. The method includes forming an electrode layer including a gate electrode, a source electrode and a drain electrode spaced apart one another. The method includes forming a dielectric layer covering the gate electrode, the source electrode, the drain electrode and the buffer layer.

Abstract: A fabrication method for fabricating a thin-film transistor includes: forming a light shielding layer on a substrate; forming a buffer layer covering the light shielding layer, and forming a semiconductor material layer stacked on a surface of the buffer layer away from the substrate; forming a through hole penetrating through the buffer layer and the semiconductor material layer; patterning the semiconductor material layer to form an active layer covering a partial region of the buffer layer; forming a gate insulator layer on a surface of the active layer away from the substrate and a gate stacked on a surface of the gate insulator layer away from the substrate; forming a source and a drain on the surface of the buffer layer away from the substrate; and forming a dielectric layer covering the gate, the source, the drain, and the buffer layer, and being recessed into the through hole to form a groove.

Abstract: The present disclosure provides a method for determining a width-to-length ratio of a channel region of a thin film transistor (TFT). The method includes: S1, setting an initial width-to-length ratio of the channel region; S2, manufacturing a TFT by using a mask plate according to the initial width-to-length ratio; S3, testing the TFT manufactured according to the initial width-to-length ratio; S4, determining whether or not the test result satisfies a predetermined condition, performing S5 if the test result satisfies the predetermined condition, and performing S6 if the test result does not satisfy the predetermined condition; S5, determining the initial width-to-length ratio as the width-to-length ratio of the channel region of the TFT; S6, changing the value of the initial width-to-length ratio, adjusting a position of the mask plate according to the changed initial width-to-length ratio, and performing S2 to S4 again.