Patents by Inventor Chan-Hong Chern
Chan-Hong Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240145587Abstract: A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.Type: ApplicationFiled: January 9, 2024Publication date: May 2, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Jun-De Jin, Chan-Hong Chern
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Patent number: 11973078Abstract: Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.Type: GrantFiled: February 1, 2023Date of Patent: April 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventor: Chan-Hong Chern
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Patent number: 11955956Abstract: A switching circuit includes a main circuit including a number of first transistors. The main circuit has a first node, a second node, and a third node and is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. The switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit. The auxiliary circuit includes a second transistor. A breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the number of first transistors.Type: GrantFiled: June 8, 2022Date of Patent: April 9, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-An Lai, Chan-Hong Chern, Cheng-Hsiang Hsieh
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Publication number: 20240085472Abstract: An integrated circuit includes a first circuit, formed based on one or more Group III-V compound materials, that is configured to operate with a first voltage range. The integrated circuit includes a second circuit, also formed based on the one or more Group III-V compound materials, that is operatively coupled to the first circuit and configured to operate with a second voltage range, wherein the second voltage range is substantially higher than the first voltage range. The integrated circuit includes a set of first test terminals connected to the first circuit. The integrated circuit includes a set of second test terminals connected to the second circuit. Test signals applied to the set of first test terminals and to the set of second test terminals, respectively, are independent from each other.Type: ApplicationFiled: November 21, 2023Publication date: March 14, 2024Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Yi-An Lai, Chan-Hong Chern, Cheng-Hsiang Hsieh
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Publication number: 20240069278Abstract: A semiconductor structure including a semiconductor waveguide layer over a second dielectric layer and between sidewalls of a first dielectric layer. A first cladding layer is between the sidewalls of the first dielectric layer and directly over the semiconductor waveguide layer. A second cladding layer is between sidewalls of the second dielectric layer and directly under the semiconductor waveguide layer. A difference between a refractive index of the semiconductor waveguide layer and a refractive index of the first cladding layer is less than a difference between the refractive index of the semiconductor waveguide layer and a refractive index of the first dielectric layer. A difference between the refractive index of the semiconductor waveguide layer and a refractive index of the second cladding layer is less than a difference between the refractive index of the semiconductor waveguide layer and a refractive index of the second dielectric layer.Type: ApplicationFiled: August 25, 2022Publication date: February 29, 2024Inventor: Chan-Hong Chern
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Patent number: 11888055Abstract: A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.Type: GrantFiled: June 14, 2021Date of Patent: January 30, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Jun-De Jin, Chan-Hong Chern
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Patent number: 11874538Abstract: A directional coupler is configured to receive a continuous light waveform and split the waveform into two carrier signals. Ring modulators are configured to receive the carrier signals and binary data and modulate the carrier signals based on the binary data. A combiner is configured to combine the modulated carrier signals into a four-level pulse amplitude modulation (PAM4) signal.Type: GrantFiled: September 30, 2020Date of Patent: January 16, 2024Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITEDInventors: Chih-Chang Lin, Chan-Hong Chern
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Patent number: 11860421Abstract: An optical system with different optical coupling device configurations and a method of fabricating the same are disclosed. An optical system includes a substrate, a waveguide disposed on the substrate, an optical fiber optically coupled to the waveguide, and an optical coupling device disposed between the optical fiber and the waveguide. The optical coupling device configured to optically couple the optical fiber to the waveguide. The optical coupling device includes a dielectric layer disposed on the substrate, a semiconductor tapered structure disposed in a first horizontal plane within the dielectric layer, and a multi-tip dielectric structure disposed in a second horizontal plane within the dielectric layer. The first and second horizontal planes are different from each other.Type: GrantFiled: November 13, 2020Date of Patent: January 2, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Weiwei Song, Chan-Hong Chern, Chewn-Pu Jou, Stefan Rusu, Min-Hsiang Hsu
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Patent number: 11852675Abstract: An integrated circuit includes a first circuit, formed based on one or more Group III-V compound materials, that is configured to operate with a first voltage range. The integrated circuit includes a second circuit, also formed based on the one or more Group III-V compound materials, that is operatively coupled to the first circuit and configured to operate with a second voltage range, wherein the second voltage range is substantially higher than the first voltage range. The integrated circuit includes a set of first test terminals connected to the first circuit. The integrated circuit includes a set of second test terminals connected to the second circuit. Test signals applied to the set of first test terminals and to the set of second test terminals, respectively, are independent from each other.Type: GrantFiled: May 5, 2022Date of Patent: December 26, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Yi-An Lai, Chan-Hong Chern, Cheng-Hsiang Hsieh
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Publication number: 20230400639Abstract: Disclosed are edge couplers having a high coupling efficiency and low polarization dependent loss, and methods of making the edge couplers. In one embodiment, a semiconductor device for optical coupling is disclosed. The semiconductor device includes: a substrate; an optical waveguide over the substrate; and a plurality of layers over the optical waveguide. The plurality of layers includes a plurality of coupling pillars disposed at an edge of the semiconductor device. The plurality of coupling pillars form an edge coupler configured for optically coupling the optical waveguide to an optical fiber placed at the edge of the semiconductor device.Type: ApplicationFiled: August 9, 2023Publication date: December 14, 2023Inventors: Min-Hsiang HSU, Chewn-Pu Jou, Chan-Hong Chern, Cheng-Tse Tang, Yung-Jr Hung, Lan-Chou Cho
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Publication number: 20230403001Abstract: A switching circuit includes a main circuit including a number of first transistors. The main circuit has a first node, a second node, and a third node and is operative in response to a control signal received by the first node, and the second node is configured to receive a supply voltage. The switching circuit also includes an auxiliary circuit electrically coupled to the second node of the main circuit and configured to provide surge protection for the main circuit. The auxiliary circuit includes a second transistor. A breakdown voltage of the second transistor is different than a breakdown voltage of each first transistor of the number of first transistors.Type: ApplicationFiled: June 8, 2022Publication date: December 14, 2023Inventors: Yi-An Lai, Chan-Hong Chern, Cheng-Hsiang Hsieh
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Publication number: 20230400647Abstract: Disclosed are apparatus and methods for optical coupling in optical communications. In one embodiment, an apparatus for optical coupling is disclosed. The apparatus includes: a planar layer; an array of scattering elements arranged in the planar layer at a plurality of intersections of a first set of concentric elliptical curves crossing with a second set of concentric elliptical curves rotated proximately 90 degrees to form a two-dimensional (2D) grating; a first taper structure formed in the planar layer connecting a first convex side of the 2D grating to a first waveguide; and a second taper structure formed in the planar layer connecting a second convex side of the 2D grating to a second waveguide. Each scattering element is a pillar into the planar layer. The pillar has a top surface whose shape is a concave polygon having at least 6 corners.Type: ApplicationFiled: August 9, 2023Publication date: December 14, 2023Inventors: Chan-Hong CHERN, Min-Hsiang HSU
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Patent number: 11841561Abstract: A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.Type: GrantFiled: July 19, 2021Date of Patent: December 12, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Weiwei Song, Stefan Rusu, Chan-Hong Chern, Chih-Chang Lin
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Publication number: 20230395583Abstract: A semiconductor package includes a photonic die having a first side and a second side opposite to each other. The semiconductor package includes an electrical die having a third side and a fourth side opposite to each other. The first side of the photonic die faces the third side of the electrical die. The photonic die has an index matching material extending from a surface of the photonic die on the second side into the photonic die.Type: ApplicationFiled: June 7, 2022Publication date: December 7, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chan-Hong Chern
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Publication number: 20230396238Abstract: Systems, methods, and devices are described herein for generating a pulse width modulation (PWM) signal having a specific duty cycle. In one embodiment, the system includes a square wave generator and a logic device. The square wave generator is configured to delay a input square wave signal to generate a plurality of square wave signals. The logic device is configured to perform a logic operation to two of square wave signals of the plurality of square wave signals, which in turn generates the PWM signal having a duty cycle corresponding to the two square wave signals.Type: ApplicationFiled: August 8, 2023Publication date: December 7, 2023Inventors: Yi-An Lai, Chan-Hong Chern, Cheng-Hsiang Hsieh
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Publication number: 20230395694Abstract: An efficient AlGaN/GaN High Electron Mobility Transistor (HEMT) device suitable for use in high frequency and high power applications is disclosed. By including a second AlGaN layer that is selectively deposited outside the gate region, it is possible to reduce on-resistance of the device without affecting the threshold voltage. Independent control of Rds-on and threshold voltage Vth can therefore be achieved, resulting in enhanced performance.Type: ApplicationFiled: March 23, 2023Publication date: December 7, 2023Applicant: Taiwan Semiconductor Manufacturing Co., Lid.Inventors: Chan-Hong CHERN, Yi-An LAI
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Publication number: 20230375862Abstract: A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.Type: ApplicationFiled: August 1, 2023Publication date: November 23, 2023Inventors: Weiwei Song, Stefan Rusu, Chan-Hong Chern, Chih-Chang Lin
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Publication number: 20230378385Abstract: A photodetector is provided. The photodetector includes a cathode electrode in a semiconductor layer, a light absorption material at least partially embedded in the semiconductor layer, an anode electrode over the light absorption material, and a lower buffer layer electrically connecting between the cathode electrode and the light absorption material. The lower buffer layer includes first SiGe layers vertically stacked and spaced apart from each other, and atomic percentages of germanium in the first SiGe layers increase in order as a level of a first SiGe layer increases from bottom to top.Type: ApplicationFiled: July 28, 2023Publication date: November 23, 2023Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.Inventor: Chan-Hong CHERN
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Publication number: 20230378384Abstract: The present disclosure provides a photo sensing device and a method of forming the same. The photo sensing device includes a substrate comprising a silicon layer at a front surface of the substrate; a photosensitive member extending into and at least partially surrounded by the silicon layer, and a composite layer disposed between the photosensitive member and the silicon layer and surrounding the photosensitive member. The silicon layer includes a first doped region adjacent to a first side of the photosensitive member and a second doped region adjacent to a second side of the photosensitive member opposite to the first side. The first doped region has a first conductivity type and includes a heavily doped region and a lightly doped region adjacent to the heavily doped region. The second doped region has a second conductivity type different from the first conductivity type.Type: ApplicationFiled: August 3, 2023Publication date: November 23, 2023Inventor: CHAN-HONG CHERN
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Patent number: 11824129Abstract: The present disclosure provides a photo sensing device including a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, wherein the silicon layer includes a first doped region adjacent to a first side of the photosensitive member, wherein the first doped region has a first conductivity type, and a second doped region adjacent to a second side of the photosensitive member opposite to the first side, wherein the second doped region has a second conductivity type different from the first conductivity type, and a composite layer disposed between the photosensitive member and the silicon layer and surrounding the photosensitive member, and a portion of the composite layer proximal to the first doped region is doped with a dopant having the first conductivity type.Type: GrantFiled: June 24, 2022Date of Patent: November 21, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LTD.Inventor: Chan-Hong Chern