Patents by Inventor Chan-Hong Chern

Chan-Hong Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10804895
    Abstract: Devices are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.
    Type: Grant
    Filed: April 24, 2019
    Date of Patent: October 13, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Chu Fu Chen, Chun Lin Tsai, Mark Chen, King-Yuen Wong, Ming-Cheng Lin, Tysh-Bin Lin
  • Publication number: 20200304119
    Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.
    Type: Application
    Filed: June 10, 2020
    Publication date: September 24, 2020
    Inventors: Chan-Hong Chern, Tysh-Bin Liu, Kun-Lung Chen
  • Publication number: 20200287528
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.
    Type: Application
    Filed: May 26, 2020
    Publication date: September 10, 2020
    Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Publication number: 20200274535
    Abstract: A circuit receives an input signal that switches between reference and first voltage levels, a power node carries a second voltage level, and a set of transistors is coupled between the power node and an output node. The second voltage level is a multiple of the first voltage level, and the multiple and a number of the transistors have a same value greater than two. A control signal circuit includes a level shifting circuit including a series of capacitive devices paired with latch circuits, a number of the pairs being one less than the value of the multiple, and, responsive to the input signal, outputs a control signal to a gate of a transistor of the first set of transistors closest to the power node, the control signal switching between the second voltage level and a third voltage level equal to the second voltage level minus the first voltage level.
    Type: Application
    Filed: May 14, 2020
    Publication date: August 27, 2020
    Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Publication number: 20200228116
    Abstract: Devices are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.
    Type: Application
    Filed: March 26, 2020
    Publication date: July 16, 2020
    Inventors: Chan-Hong Chern, Chu Fu Chen, Chun Lin Tsai, Mark Chen, King-Yuen Wong, Ming-Cheng Lin, Tysh-Bin Lin
  • Patent number: 10715137
    Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.
    Type: Grant
    Filed: October 19, 2018
    Date of Patent: July 14, 2020
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Tysh-Bin Liu, Kun-Lung Chen
  • Patent number: 10686434
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.
    Type: Grant
    Filed: November 30, 2018
    Date of Patent: June 16, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 10673437
    Abstract: A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.
    Type: Grant
    Filed: January 7, 2019
    Date of Patent: June 2, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Publication number: 20200161463
    Abstract: Apparatus and circuits including transistors with different polarizations and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion and a second active portion; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first active portion has a material composition different from that of the second active portion.
    Type: Application
    Filed: October 15, 2019
    Publication date: May 21, 2020
    Inventor: Chan-Hong CHERN
  • Publication number: 20200135911
    Abstract: Apparatus and circuits with dual polarization transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.
    Type: Application
    Filed: September 19, 2019
    Publication date: April 30, 2020
    Inventor: Chan-Hong CHERN
  • Publication number: 20200135910
    Abstract: Apparatus and circuits including transistors with different gate stack materials and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a channel layer formed over the substrate; a first transistor formed over the channel layer, wherein the first transistor comprises a first source region, a first drain region, a first gate structure, and a first polarization modulation portion under the first gate structure; and a second transistor formed over the channel layer, wherein the second transistor comprises a second source region, a second drain region, a second gate structure, and a second polarization modulation portion under the second gate structure, wherein the first polarization modulation portion is made of a material different from that of the second polarization modulation portion.
    Type: Application
    Filed: September 19, 2019
    Publication date: April 30, 2020
    Inventor: Chan-Hong CHERN
  • Publication number: 20200132558
    Abstract: A circuit includes a temperature-sensitive voltage divider. The temperature-sensitive voltage divider includes a temperature-sensitive resistor and a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor. A temperature signal is generated at a first node coupled to the first terminal of the temperature-sensitive resistor. Detection logic is coupled to the first node to generate a detection signal responsive to the temperature signal.
    Type: Application
    Filed: July 1, 2019
    Publication date: April 30, 2020
    Inventors: Chan-Hong CHERN, Kun-Lung CHEN, Ming Hsien TSAI
  • Publication number: 20200135722
    Abstract: Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.
    Type: Application
    Filed: September 19, 2019
    Publication date: April 30, 2020
    Inventor: Chan-Hong CHERN
  • Publication number: 20200135733
    Abstract: Apparatus and circuits with dual threshold voltage transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a first layer comprising a first III-V semiconductor material formed over the substrate; a first transistor formed over the first layer, and a second transistor formed over the first layer. The first transistor comprises a first gate structure comprising a first material, a first source region and a first drain region. The second transistor comprises a second gate structure comprising a second material, a second source region and a second drain region. The first material is different from the second material.
    Type: Application
    Filed: September 19, 2019
    Publication date: April 30, 2020
    Inventor: Chan-Hong CHERN
  • Publication number: 20200091895
    Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.
    Type: Application
    Filed: November 25, 2019
    Publication date: March 19, 2020
    Inventors: Chan-Hong Chern, Kun-Lung Chen
  • Publication number: 20200066685
    Abstract: Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Inventors: Chan-Hong Chern, Mark Chen
  • Patent number: 10546528
    Abstract: A current value of a first pixel and/or a current value of a second pixel of a display are adjusted until a value of a current difference is within a predetermined range. The current value of the first pixel corresponds to a brightness level of the first pixel. The current value of the second pixel corresponds to a brightness level of the second pixel. Adjusting the current value of the first pixel involves adjusting a threshold voltage value of a transistor of the first pixel. Adjusting the current value of the second pixel involves adjusting a threshold voltage value of a transistor of the second pixel.
    Type: Grant
    Filed: August 14, 2015
    Date of Patent: January 28, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching Huang, Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin
  • Patent number: 10536146
    Abstract: An edge detector includes an output node selectively coupled to a first voltage node through a first transistor, the first voltage node having a first voltage level, and a second transistor configured to continuously couple the output node to a second voltage node having a second voltage level. A capacitor includes a first terminal coupled to a gate of the first transistor and a second terminal configured to receive an input signal.
    Type: Grant
    Filed: May 17, 2019
    Date of Patent: January 14, 2020
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
  • Patent number: 10523183
    Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.
    Type: Grant
    Filed: September 25, 2018
    Date of Patent: December 31, 2019
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Kun-Lung Chen
  • Patent number: 10504874
    Abstract: Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Mark Chen