Patents by Inventor Chan-Hong Chern

Chan-Hong Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210396930
    Abstract: A semiconductor structure according to the present disclosure includes a buried oxide layer, a first dielectric layer disposed over the buried oxide layer, a first waveguide feature disposed in the first dielectric layer, a second dielectric layer disposed over the first dielectric layer and the first waveguide feature, a third dielectric layer disposed over the second dielectric layer, and a second waveguide feature disposed in the second dielectric layer and the third dielectric layer. The second waveguide feature is disposed over the second waveguide feature and a portion of the second waveguide feature vertically overlaps a portion of the first waveguide feature.
    Type: Application
    Filed: March 25, 2021
    Publication date: December 23, 2021
    Inventors: Chan-Hong Chern, Lan-Chou Cho, Huan-Neng Chen, Min Hsiang Hsu, Feng-Wei Kuo, Chih-Chang Lin, Weiwei Song, Chewn-Pu Jou
  • Publication number: 20210372859
    Abstract: A circuit includes a temperature-sensitive voltage divider. The temperature-sensitive voltage divider includes a temperature-sensitive resistor and a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor. A temperature signal is generated at a first node coupled to the first terminal of the temperature-sensitive resistor. Detection logic is coupled to the first node to generate a detection signal responsive to the temperature signal.
    Type: Application
    Filed: August 16, 2021
    Publication date: December 2, 2021
    Inventors: Chan-Hong CHERN, Kun-Lung CHEN, Ming Hsien TSAI
  • Patent number: 11189719
    Abstract: Apparatus and circuits including transistors with different gate stack materials and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; a channel layer formed over the substrate; a first transistor formed over the channel layer, wherein the first transistor comprises a first source region, a first drain region, a first gate structure, and a first polarization modulation portion under the first gate structure; and a second transistor formed over the channel layer, wherein the second transistor comprises a second source region, a second drain region, a second gate structure, and a second polarization modulation portion under the second gate structure, wherein the first polarization modulation portion is made of a material different from that of the second polarization modulation portion.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: November 30, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chan-Hong Chern
  • Patent number: 11169328
    Abstract: A photonic structure is provided. The photonic structure includes a semiconductor substrate, a buried oxide layer over the semiconductor substrate, an optical coupling region over the buried oxide layer, and an oxide structure embedded in the semiconductor substrate. The optical coupling region is tapered toward a terminus of the optical coupling region located at an edge of the semiconductor substrate. The optical coupling region overlaps the oxide structure in a plan view.
    Type: Grant
    Filed: July 2, 2020
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Min-Hsiang Hsu
  • Publication number: 20210341766
    Abstract: An optical phase-shifting device includes a ribbed waveguide portion on an insulating layer, the waveguide portion having a p-n or p-i-n junction extending in a longitudinal direction and having a height. A pair of slab portions are disposed adjacent the waveguide portion, one on each side of the ribbed waveguide portion and on the insulation layer. The slab portion have higher doping concentrations than the respective doping concentrations in the ribbed waveguide portion. At least a portion of each slab portion has a height increasing with distance from the waveguide portion, with the slab height being smaller than that of the waveguide portion at the junction between the waveguide portion and slab portion. A pair of contact portions are formed adjacent the respective slab portion and further away from the waveguide portion. A portion of each contact portion can also have a height varying with distance from the waveguide portion.
    Type: Application
    Filed: May 4, 2020
    Publication date: November 4, 2021
    Inventor: Chan-Hong Chern
  • Publication number: 20210305419
    Abstract: A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.
    Type: Application
    Filed: June 14, 2021
    Publication date: September 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Jun-De Jin, Chan-Hong Chern
  • Publication number: 20210302650
    Abstract: Methods of fabricating optical devices with high refractive index materials are disclosed. The method includes forming a first oxide layer on a substrate and forming a patterned template layer with first and second trenches on the first oxide layer. A material of the patterned template layer has a first refractive index. The method further includes forming a first portion of a waveguide and a first portion of an optical coupler within the first and second trenches, respectively, forming a second portion of the waveguide and a second portion of the optical coupler on a top surface of the patterned template layer, and depositing a cladding layer on the second portions of the waveguide and optical coupler. The waveguide and the optical coupler include materials with a second refractive index that is greater than the first refractive index.
    Type: Application
    Filed: January 15, 2021
    Publication date: September 30, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Weiwei SONG, Chan-Hong Chern, Chih-Chang Lin, Stefan Rusu, Min-Hsiang Hsu
  • Patent number: 11128285
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, a second power node configured to carry a second voltage having a second voltage level, an output node, and first and second cascode transistors coupled between the first power node and the output node and to each other at a node. A bias circuit uses the first and second cascode transistors to generate an output signal at the output node that transitions between the first voltage level and a third voltage level, and a delay circuit generates a transition in a first signal from one of the first or second voltage levels to the other of the first or second voltage levels, the transition having a time delay based on the output signal. A contending transistor couples the node to the second power node responsive to the first signal.
    Type: Grant
    Filed: May 26, 2020
    Date of Patent: September 21, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Publication number: 20210281259
    Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.
    Type: Application
    Filed: May 24, 2021
    Publication date: September 9, 2021
    Inventors: Chan-Hong Chern, Tysh-Bin Liu, Kun-Lung Chen
  • Publication number: 20210280580
    Abstract: Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.
    Type: Application
    Filed: May 26, 2021
    Publication date: September 9, 2021
    Inventor: Chan-Hong CHERN
  • Patent number: 11092497
    Abstract: A circuit includes a temperature-sensitive voltage divider. The temperature-sensitive voltage divider includes a temperature-sensitive resistor and a second resistor having a first terminal coupled to a first terminal of the temperature-sensitive resistor. A temperature signal is generated at a first node coupled to the first terminal of the temperature-sensitive resistor. Detection logic is coupled to the first node to generate a detection signal responsive to the temperature signal.
    Type: Grant
    Filed: July 1, 2019
    Date of Patent: August 17, 2021
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventors: Chan-Hong Chern, Kun-Lung Chen, Ming Hsien Tsai
  • Publication number: 20210231869
    Abstract: Integrated optical devices and methods of forming the same are disclosed. A method of forming an integrated optical device includes the following steps. A substrate is provided. The substrate includes, from bottom to top, a first semiconductor layer, an insulating layer and a second semiconductor layer. The second semiconductor layer is patterned to form a waveguide pattern. A surface smoothing treatment is performed to the waveguide pattern until a surface roughness Rz of the waveguide pattern is equal to or less than a desired value. A cladding layer is formed over the waveguide pattern.
    Type: Application
    Filed: April 14, 2021
    Publication date: July 29, 2021
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Min-Hsiang Hsu
  • Publication number: 20210226611
    Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventors: Chan-Hong Chern, Kun-Lung Chen
  • Publication number: 20210226049
    Abstract: Apparatus and circuits with dual polarization transistors and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a first active portion having a first thickness and a second active portion having a second thickness; a first transistor comprising a first source region, a first drain region, and a first gate structure formed over the first active portion and between the first source region and the first drain region; and a second transistor comprising a second source region, a second drain region, and a second gate structure formed over the second active portion and between the second source region and the second drain region, wherein the first thickness is different from the second thickness.
    Type: Application
    Filed: April 5, 2021
    Publication date: July 22, 2021
    Inventor: Chan-Hong CHERN
  • Publication number: 20210193564
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.
    Type: Application
    Filed: August 4, 2020
    Publication date: June 24, 2021
    Inventors: Weiwei Song, Chan-Hong Chern, Feng-Wei Kuo, Lan-Chou Cho, Stefan Rusu
  • Patent number: 11038048
    Abstract: A gallium nitride-on-silicon structure is disclosed in which the two-dimensional electron gas (2DEG) layer is a discontinuous layer that includes at least two 2DEG segments. Each 2DEG segment is separated from another 2DEG segment by a gap. The 2DEG layer can be depleted by a p-doped gallium nitride layer that is disposed over a portion of an aluminum gallium nitride layer. Additionally or alternatively, a trench may be formed in the structure through the 2DEG layer to produce a gap in the 2DEG layer. An electrical component is positioned over at least a portion of a gap.
    Type: Grant
    Filed: October 1, 2019
    Date of Patent: June 15, 2021
    Inventors: Jun-De Jin, Chan-Hong Chern
  • Patent number: 11038504
    Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.
    Type: Grant
    Filed: June 10, 2020
    Date of Patent: June 15, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Tysh-Bin Liu, Kun-Lung Chen
  • Patent number: 11024626
    Abstract: Apparatus and circuits including transistors with different threshold voltages and methods of fabricating the same are disclosed. In one example, a semiconductor structure is disclosed. The semiconductor structure includes: a substrate; an active layer that is formed over the substrate and comprises a plurality of active portions; a polarization modulation layer comprising a plurality of polarization modulation portions each of which is disposed on a corresponding one of the plurality of active portions; and a plurality of transistors each of which comprises a source region, a drain region, and a gate structure formed on a corresponding one of the plurality of polarization modulation portions. The transistors have at least three different threshold voltages.
    Type: Grant
    Filed: September 19, 2019
    Date of Patent: June 1, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventor: Chan-Hong Chern
  • Patent number: 11009663
    Abstract: Integrated optical devices and methods of forming the same are disclosed. A method of forming an integrated optical device includes the following steps. A substrate is provided. The substrate includes, from bottom to top, a first semiconductor layer, an insulating layer and a second semiconductor layer. The second semiconductor layer is patterned to form a waveguide pattern. A surface smoothing treatment is performed to the waveguide pattern until a surface roughness Rz of the waveguide pattern is equal to or less than a desired value. A cladding layer is formed over the waveguide pattern.
    Type: Grant
    Filed: July 29, 2019
    Date of Patent: May 18, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Min-Hsiang Hsu
  • Patent number: 11005453
    Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.
    Type: Grant
    Filed: November 25, 2019
    Date of Patent: May 11, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Kun-Lung Chen