Patents by Inventor Chan-Hong Chern

Chan-Hong Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10504874
    Abstract: Semiconductor package structures and methods of forming the same are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: December 10, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Mark Chen
  • Publication number: 20190273500
    Abstract: An edge detector includes an output node selectively coupled to a first voltage node through a first transistor, the first voltage node having a first voltage level, and a second transistor configured to continuously couple the output node to a second voltage node having a second voltage level. A capacitor includes a first terminal coupled to a gate of the first transistor and a second terminal configured to receive an input signal.
    Type: Application
    Filed: May 17, 2019
    Publication date: September 5, 2019
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN
  • Patent number: 10401889
    Abstract: A current generator includes an amplifier having a first terminal configured to receive a first voltage, a tunable resistance circuit coupled to an output terminal of the amplifier through a first transistor, a calibration circuit coupled to the tunable resistance circuit, and a second transistor. The second transistor includes a gate terminal coupled to the output terminal of the amplifier and a drain terminal coupled to a load. The calibration circuit is configured to adjust a resistance setting of the tunable resistance circuit.
    Type: Grant
    Filed: January 6, 2016
    Date of Patent: September 3, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Chih-Chang Lin
  • Publication number: 20190253051
    Abstract: Devices are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.
    Type: Application
    Filed: April 24, 2019
    Publication date: August 15, 2019
    Inventors: Chan-Hong Chern, Chu Fu Chen, Chun Lin Tsai, Mark Chen, King-Yuen Wong, Ming-Cheng Lin, Tysh-Bin Lin
  • Publication number: 20190238119
    Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.
    Type: Application
    Filed: September 25, 2018
    Publication date: August 1, 2019
    Inventors: Chan-Hong Chern, Kun-Lung Chen
  • Patent number: 10367491
    Abstract: A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.
    Type: Grant
    Filed: June 11, 2018
    Date of Patent: July 30, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tsung-Ching (Jim) Huang, Chih-Chang Lin, Tien-Chun Yang
  • Patent number: 10298237
    Abstract: A level shifting apparatus includes a first inverter configured to receive an input signal and a second inverter capacitively coupled with an output of the first inverter, the second inverter being configured to output an output signal. A transmission gate is configured to feed back the output signal to an input of the second inverter, wherein the transmission gate is configured to selectively interrupt feedback of the output signal to the input of the second inverter.
    Type: Grant
    Filed: January 12, 2018
    Date of Patent: May 21, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching (Jim) Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
  • Publication number: 20190140645
    Abstract: A level-shifting circuit includes an input device configured to receive an input signal capable of switching between a reference voltage level and a first voltage level, and a set of capacitive devices paired in series with latch circuits. A first capacitive device of the set is coupled with an output of the input device, and each capacitive device and latch circuit pair is configured to upshift a corresponding received signal by an amount equal to a difference between the first voltage level and the reference voltage level.
    Type: Application
    Filed: January 7, 2019
    Publication date: May 9, 2019
    Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Patent number: 10284195
    Abstract: Devices, systems, and methods are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.
    Type: Grant
    Filed: June 28, 2018
    Date of Patent: May 7, 2019
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Chu Fu Chen, Chun Lin Tsai, Mark Chen, King-Yuen Wong, Ming-Cheng Lin, Tysh-Bin Lin
  • Publication number: 20190123740
    Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.
    Type: Application
    Filed: October 19, 2018
    Publication date: April 25, 2019
    Inventors: Chan-Hong Chern, Tysh-Bin Liu, Kun-Lung Chen
  • Publication number: 20190097615
    Abstract: A circuit includes a first power node configured to carry a first voltage having a first voltage level, an output node, a node coupled between the first power node and the output node, and a contending transistor coupled between the node and a second power node configured to carry a second voltage having a second voltage level. The circuit generates a signal at the output node that ranges between the first voltage level and a third voltage level, the contending transistor couples the node with the second power node responsive to the signal, a difference between the first voltage level and the second voltage level has a first magnitude, a difference between the first voltage level and the third voltage level has a second magnitude, and the second magnitude is a multiple of the first magnitude having a value greater than one.
    Type: Application
    Filed: November 30, 2018
    Publication date: March 28, 2019
    Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Patent number: 10187046
    Abstract: A circuit includes a first power node having a first voltage level, and an output node. A driver transistor coupled between the first power and output nodes is turned on and off responsive to first and second input signal edge types, respectively. A driver transistor source is coupled with the first power node. A contending circuit includes a slew rate detection circuit that generates a feedback signal based on an output node signal, and a contending transistor between a driver transistor drain and a second voltage. A contending transistor gate receives a control signal based on the feedback signal. The second voltage has a level less than the first voltage level if the output node signal rises responsive to the first input signal edge type, and greater than the first voltage level if the output node signal falls responsive to the first input signal edge type.
    Type: Grant
    Filed: August 23, 2016
    Date of Patent: January 22, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 10177764
    Abstract: A circuit includes an output node, a set of first transistors, a set of second transistors, and a first and second power node. The first power node is configured to carry a first voltage level, and second power node is configured to carry a second voltage level. Set of first transistors is coupled between the first power node and output node. Set of second transistors is coupled between the second power node and output node. The first control signal generating circuit is coupled to a gate of a first transistor of the set of first transistors and a gate of a first transistor of the set of second transistors. The first control signal generating circuit is configured to generate a set of biasing signals for the gate of the first transistor of the set of first transistors and the gate of the first transistor of the set of second transistors.
    Type: Grant
    Filed: January 12, 2017
    Date of Patent: January 8, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Publication number: 20180316346
    Abstract: Devices, systems, and methods are described herein for a low static current semiconductor device. A semiconductor device includes a power transistor and a driving circuit coupled to and configured to drive the power transistor. The driving circuit includes a first stage having an enhancement-mode high-electron-mobility transistor (HEMT) and a a second stage that is coupled between the first stage and the power transistor and that includes a pair of enhancement-mode HEMTs.
    Type: Application
    Filed: June 28, 2018
    Publication date: November 1, 2018
    Inventors: Chan-Hong Chern, Chu Fu Chen, Chun Lin Tsai, Mark Chen, King-Yuen Wong, Ming-Cheng Lin, Tysh-Bin Lin
  • Publication number: 20180294803
    Abstract: A delay line circuit including: a coarse-tuning arrangement, including delay units, the coarse-tuning arrangement being configured to coarsely-tune an input signal by transferring the input signal through a selected number of the delay units and thereby producing a first output signal; and a fine-tuning arrangement configured to receive the first output signal at a beginning of a signal path which includes at least three serially-connected inverters, finely-tune the first output signal along the signal path, and produce a second output signal at an end of the signal path; the fine-tuning arrangement including: a speed control unit which is selectively-connectable, and a switching circuit to selectively connect the speed control unit to the signal path based on a process-corner signal.
    Type: Application
    Filed: June 11, 2018
    Publication date: October 11, 2018
    Inventors: Ming-Chieh HUANG, Chan-Hong CHERN, Tsung-Ching (Jim) HUANG, Chih-Chang LIN, Tien-Chun YANG
  • Patent number: 10083856
    Abstract: Semiconductor structures including isolation regions and methods of forming the same are provided. A first layer is formed over a substrate, where the first layer comprises a semiconductor material. First and second trenches are etched, with each of the first and second trenches extending through the first layer and into the substrate. A wet etchant is introduced into the trenches, and the wet etchant etches a first opening below the first trench and a second opening below the second trench. Each of the first and second openings extends laterally below the first layer. The first and second openings are separated by a portion of the substrate adjoining the first and second openings. An oxidation process is performed to oxidize the portion of the substrate adjoining the first and second openings. An insulating material is deposited that fills the openings and the trenches.
    Type: Grant
    Filed: August 1, 2016
    Date of Patent: September 25, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Chun-Lin Tsai, Mark Chen, King-Yuen Wong
  • Publication number: 20180241380
    Abstract: A latch circuit includes a power supply node, first and second input nodes, and first and second output nodes. A first switching device is coupled between the first and second output nodes and is turned on and off in response to respective first and second states of a clock signal. A first transistor has a source coupled with a common node, a drain coupled with the second output node, and a gate directly coupled with the first input node, and a second transistor has a source coupled with the common node, a drain coupled with the first output node, and a gate directly coupled with the second input node. A second switching device is coupled between the common node and the power supply node and is turned on and off in response to the respective second and first states of the clock signal.
    Type: Application
    Filed: April 24, 2018
    Publication date: August 23, 2018
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN, Tien-Chun YANG
  • Patent number: 10050621
    Abstract: A semiconductor device includes a power transistor and a driving circuit. The driving circuit is coupled to and is configured to drive the power transistor and includes first and second stages. The second stage is coupled between the first stage and the power transistor. Each of the first and second stages includes a pair of enhancement-mode high-electron-mobility transistors (HEMTs). The construction as such lowers a static current of the driving circuit.
    Type: Grant
    Filed: September 29, 2016
    Date of Patent: August 14, 2018
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Chu Fu Chen, Chun Lin Tsai, Mark Chen, King-Yuen Wong, Ming-Cheng Lin, Tysh-Bin Liu
  • Patent number: 9998103
    Abstract: A delay line circuit includes: a coarse-tuning arrangement, including delay units; and a fine-tuning arrangement including at least three serially-connected inverters. The coarse-tuning arrangement is configured to receive an input signal and coarsely-tune the input signal, the coarsely-tuning including transferring the input signal through a selected number of the delay units and thereby producing a first output signal. The fine-tuning arrangement is configured to receive the first output signal, finely-tune the first output signal, and produce a second output signal, the finely-tuning including selectively connecting a speed control unit to a node between a corresponding pair of the at least three serially-connected inverters.
    Type: Grant
    Filed: January 24, 2017
    Date of Patent: June 12, 2018
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tsung-Ching (Jim) Huang, Chih-Chang Lin, Tien-Chun Yang
  • Publication number: 20180138909
    Abstract: A level shifting apparatus includes a first inverter configured to receive an input signal and a second inverter capacitively coupled with an output of the first inverter, the second inverter being configured to output an output signal. A transmission gate is configured to feed back the output signal to an input of the second inverter, wherein the transmission gate is configured to selectively interrupt feedback of the output signal to the input of the second inverter.
    Type: Application
    Filed: January 12, 2018
    Publication date: May 17, 2018
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN