Patents by Inventor Chan-Hong Chern

Chan-Hong Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9529955
    Abstract: A layout of a portion of an integrated circuit includes first and second cell structures, each including a first or second dummy gate electrode disposed on a first or second boundary of the corresponding first or second cell structure, a first or second edge gate electrode disposed adjacent to the corresponding first or second dummy gate electrode, and a first or second oxide definition (OD) region having a first or second edge. The second boundary faces the first boundary without abutting the first boundary. The first edge of the first OD region is substantially aligned with the closest edge of the first dummy gate electrode or overlaps the first dummy gate electrode. A distance from the first edge gate electrode to the farthest edge of the first dummy gate electrode is greater than the distance from the first edge gate electrode to the first edge of the first OD region.
    Type: Grant
    Filed: December 19, 2013
    Date of Patent: December 27, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Li-Chun Tien
  • Patent number: 9524934
    Abstract: A method of forming an integrated circuit includes forming at least one transistor over a substrate. Forming the at least one transistor includes forming a gate dielectric structure over a substrate. A work-function metallic layer is formed over the gate dielectric structure. A conductive layer is formed over the work-function metallic layer. A source/drain (S/D) region is formed adjacent to each sidewall of the gate dielectric structure. At least one electrical fuse is formed over the substrate. Forming the at least one electrical fuse includes forming a first semiconductor layer over the substrate. A first silicide layer is formed on the first semiconductor layer.
    Type: Grant
    Filed: November 22, 2011
    Date of Patent: December 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Kuoyuan (Peter) Hsu
  • Publication number: 20160359475
    Abstract: A circuit includes a first power node having a first voltage level, and an output node. A driver transistor coupled between the first power and output nodes is turned on and off responsive to first and second input signal edge types, respectively. A driver transistor source is coupled with the first power node. A contending circuit includes a slew rate detection circuit that generates a feedback signal based on an output node signal, and a contending transistor between a driver transistor drain and a second voltage. A contending transistor gate receives a control signal based on the feedback signal. The second voltage has a level less than the first voltage level if the output node signal rises responsive to the first input signal edge type, and greater than the first voltage level if the output node signal falls responsive to the first input signal edge type.
    Type: Application
    Filed: August 23, 2016
    Publication date: December 8, 2016
    Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Patent number: 9509260
    Abstract: A transimpedance amplifier includes a first inverter having a first input node and a first output node. The first input node is configured to receive an input signal. A second inverter has a second input node and a second output node. The second input node connects to a reference voltage terminal. The first inverter and the second inverter are configured to provide a differential output voltage signal between the first output node and the second output node. A first amplifier is configured to provide feedback to the first input node and a second amplifier is configured to provide feedback to the second input node.
    Type: Grant
    Filed: October 1, 2014
    Date of Patent: November 29, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching Huang, Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin
  • Patent number: 9503252
    Abstract: Some embodiments relate to a phase interpolator. The phase interpolator includes a control block to provide a plurality of phase interpolation control signals which are collectively indicative of a phase difference between a first clock and a second clock. The phase interpolation control signals define different phase step sizes by which the first clock is to be phase shifted to limit the phase difference. A plurality of Gilbert cells provide a plurality of current levels, respectively, based on the plurality of phase interpolation control signals. A plurality of current control elements adjust the plurality of current levels from the plurality of Gilbert cells. The plurality of current levels are adjusted by different amounts for the different phase step sizes.
    Type: Grant
    Filed: January 27, 2014
    Date of Patent: November 22, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tao Wen (David) Chung, Tsung-Ching (Jim) Huang, Chih-Chang Lin
  • Patent number: 9502098
    Abstract: A method of operating a first voltage regulator includes electrically coupling a transistor of an output stage of the first voltage regulator between a first power voltage and a second power voltage, and reverse biasing a bulk of the transistor by a back-bias circuit during a standby mode of a memory array. The first voltage regulator is coupled to a second voltage regulator and reverse biasing the bulk of the transistor reduces a contention current between the first voltage regulator and the second voltage regulator.
    Type: Grant
    Filed: February 3, 2016
    Date of Patent: November 22, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tien Chun Yang, Chih-Chang Lin, Yuwen Swei
  • Patent number: 9489989
    Abstract: A voltage regulator includes an output stage electrically coupled with an output end of the voltage regulator. The output stage includes at least one transistor having a bulk and a drain. At least one back-bias circuit is electrically coupled with the bulk of the at least one transistor. The at least one back-bias circuit is configured to provide a bulk voltage, such that the bulk and the drain of the at least one transistor are reverse biased during a standby mode of a memory array that is electrically coupled with the voltage regulator.
    Type: Grant
    Filed: June 22, 2010
    Date of Patent: November 8, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Chan-Hong Chern, Tien Chun Yang, Chih-Chang Lin, Yuwen Swei
  • Patent number: 9461539
    Abstract: A voltage regulator includes a driving circuit, a feedback circuit, first and second control circuits and a resistor. The driving circuit is coupled to an input node and an output node and generates an output voltage at the output node from an input voltage at the input node. The feedback circuit is coupled to the output node and generates a feedback voltage based on the output voltage. The first control circuit is coupled to the feedback circuit and the driving circuit to control the output voltage based on the feedback voltage. The resistor has opposite first and second terminals. The first terminal of the resistor is coupled to the output node. The second control circuit is coupled to the second terminal of the output stage resistor and the feedback circuit to control the feedback voltage based on a regulated voltage at the second terminal of the resistor.
    Type: Grant
    Filed: March 15, 2013
    Date of Patent: October 4, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching (Jim) Huang
  • Patent number: 9455666
    Abstract: A circuit includes at least two LC voltage controlled oscillators (LCVCOs). Each LCVCO includes a switch to selectively turn on or off the LCVCO. One selected LCVCO of the at least two LCVCOs is configured to provide a differential LCVCO output. A converter coupled to the at least two LCVCOs is configured to receive the differential LCVCO output and provide an output signal with a full voltage swing.
    Type: Grant
    Filed: February 13, 2015
    Date of Patent: September 27, 2016
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chih-Chang Lin, Chan-Hong Chern, Ming-Chieh Huang, Tien-Chun Yang
  • Patent number: 9450573
    Abstract: A circuit includes a first power node, an output node, a driver transistor coupled between the first power node and the output node, and a contending circuit. The driver transistor is configured to be turned on responsive to an edge of a first type of an input signal and to be turned off responsive to an edge of a second type of the input signal. The driver transistor has a source, a drain, and a gate, and the source of the driver transistor is coupled with the first power node. The contending circuit includes a control circuit configured to generate a control signal based on a signal at a gate of the driver transistor; and a contending transistor between the drain of the driver transistor and a second voltage. The contending transistor has a gate configured to receive the control signal.
    Type: Grant
    Filed: February 25, 2015
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Tsung-Ching Huang, Chih-Chang Lin, Ming-Chieh Huang, Fu-Lung Hsueh
  • Patent number: 9450789
    Abstract: An apparatus includes a plurality of delay elements configured to delay a respective input signal and to output a respective delayed signal. The apparatus also includes a weight generator configured to generate a plurality of tap weights based on the delayed signals. The apparatus further includes a tap controller configured to generate tap weight enabling signals corresponding to one or more of the tap weights if the corresponding tap weights are greater than a predetermined threshold value. The tap controller is also configured to generate a set of bias factors based on corresponding tap weights of the plurality of tap weights.
    Type: Grant
    Filed: July 9, 2015
    Date of Patent: September 20, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Chieh Huang, Jing Jing Chen, Chan-Hong Chern, Tao Wen Chung, Chih-Chang Lin, Yuwen Swei
  • Patent number: 9437257
    Abstract: A sensing circuit includes a sensing resistor, a reference resistor and a comparator. The comparator has a first input coupled to the sensing resistor, a second input coupled to the reference resistor, and an output. The first input is configured to be coupled to a data bit line associated with a memory cell to receive a sensing input voltage caused by a cell current of the memory cell flowing through the sensing resistor. The second input is configured to be coupled to a reference bit line associated with a reference cell to receive a sensing reference voltage caused by a reference current of the reference cell flowing through the reference resistor. The comparator is configured to generate, at the output, an output signal indicating a logic state of data stored in the memory cell based on a comparison between the sensing input voltage and the sensing reference voltage.
    Type: Grant
    Filed: February 12, 2013
    Date of Patent: September 6, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tien-Chun Yang, Yue-Der Chih, Chan-Hong Chern, Tao Wen Chung
  • Publication number: 20160248330
    Abstract: A voltage supply unit includes a regulator unit, a current mirror, and a cascode unit. The regulator unit is configured to receive first and second voltage signals and generate a third voltage signal. The current mirror is configured to generate first and second current signals based on the third voltage signal. The cascode unit includes a first terminal configured to receive the first current signal, a second terminal configured to receive a first bias voltage signal, a third terminal configured to receive a second bias voltage signal, and a fourth terminal electrically connected to the regulator unit. An output voltage supply signal is controlled by the second current signal.
    Type: Application
    Filed: May 5, 2016
    Publication date: August 25, 2016
    Inventors: Chan-Hong CHERN, Tsung-Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Publication number: 20160248411
    Abstract: A circuit includes a first power node, an output node, a driver transistor coupled between the first power node and the output node, and a contending circuit. The driver transistor is configured to be turned on responsive to an edge of a first type of an input signal and to be turned off responsive to an edge of a second type of the input signal. The driver transistor has a source, a drain, and a gate, and the source of the driver transistor is coupled with the first power node. The contending circuit includes a control circuit configured to generate a control signal based on a signal at a gate of the driver transistor; and a contending transistor between the drain of the driver transistor and a second voltage. The contending transistor has a gate configured to receive the control signal.
    Type: Application
    Filed: February 25, 2015
    Publication date: August 25, 2016
    Inventors: Chan-Hong CHERN, Tsung -Ching HUANG, Chih-Chang LIN, Ming-Chieh HUANG, Fu-Lung HSUEH
  • Publication number: 20160248408
    Abstract: A latch circuit includes a first input node, a second input node, a first output node, a second output node, a first switching device coupled between the first output node and the second output node, and a first amplification circuit coupled with the first input node, the second input node, the first output node, and the second output node. The first switching device is configured to be turned on in response to a first state of a clock signal and to be turned off in response to a second state of the clock signal. The first amplification circuit is configured to cause a voltage difference across the first switching device based on voltage levels of the first input node and the second input node in response to the first state of the clock signal.
    Type: Application
    Filed: February 25, 2015
    Publication date: August 25, 2016
    Inventors: Tsung-Ching (Jim) HUANG, Chan-Hong CHERN, Ming-Chieh HUANG, Chih-Chang LIN, Tien-Chun YANG
  • Publication number: 20160241187
    Abstract: A circuit includes at least two LC voltage controlled oscillators (LCVCOs). Each LCVCO includes a switch to selectively turn on or off the LCVCO. One selected LCVCO of the at least two LCVCOs is configured to provide a differential LCVCO output. A converter coupled to the at least two LCVCOs is configured to receive the differential LCVCO output and provide an output signal with a full voltage swing.
    Type: Application
    Filed: February 13, 2015
    Publication date: August 18, 2016
    Inventors: Chih-Chang Lin, Chan-Hong Chern, Ming-Chieh Huang, Tien-Chun Yang
  • Patent number: 9419617
    Abstract: A circuit comprises a control circuit having an output node. The circuit also comprises a half latch keeper circuit coupled to the control circuit. The half latch keeper circuit is configured to control the output node during a standby mode. The circuit also comprises a transistor coupled to the output node. The control circuit is configured to turn off the transistor during the standby mode.
    Type: Grant
    Filed: July 15, 2014
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chan-Hong Chern, Fu-Lung Hsueh, Ming-Chieh Huang, Bryan Sheffield, Chih-Chang Lin
  • Patent number: 9407218
    Abstract: A multi-stage transimpedance amplifier (TIA) which includes a common gate amplifier configured to receive a current signal, the common gate amplifier is configured to convert the current signal into an amplified voltage signal. The multi-stage TIA further includes a capacitive degeneration amplifier configured to receive the amplified voltage signal, the capacitive degeneration amplifier is configured to equalize the amplified voltage signal to form an equalized signal. The multi-stage TIA further includes an inverter configured to receive the equalized signal, the inverter is configured to increase a signal strength of the equalized signal to form an output signal. The multi-stage TIA further includes a feedback configured to receive the output signal, wherein the feedback is connected to an input and an output of the inverter.
    Type: Grant
    Filed: November 25, 2013
    Date of Patent: August 2, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Tsung-Ching Huang, Chan-Hong Chern, Ming-Chieh Huang, Chih-Chang Lin
  • Patent number: 9391626
    Abstract: A circuit includes a capacitive-load voltage controlled oscillator having an input configured to receive a first input signal and an output configured to output an oscillating output signal. A calibration circuit is coupled to the voltage controlled oscillator and is configured to output one or more control signals to the capacitive-load voltage controlled oscillator for adjusting a frequency of the oscillating output signal. The calibration circuit is configured to output the one or more control signals in response to a comparison of an input voltage to at least one reference voltage.
    Type: Grant
    Filed: August 11, 2014
    Date of Patent: July 12, 2016
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chan-Hong Chern, Tao Wen Chung, Ming-Chieh Huang, Chih-Chang Lin, Tsung-Ching Huang, Fu-Lung Hsueh
  • Patent number: RE46107
    Abstract: An integrated circuit includes a first current source. A second current source is electrically coupled with the first current source via a conductive line. A switch circuit is coupled between the first current source and the second current source. A first circuit is coupled between a first node and a second node. The first node is disposed between the first current source and the switch circuit. The second node is coupled with the first current source. The first circuit is configured for substantially equalizing voltages on the first node and the second node. A second circuit is coupled between a third node and a fourth node. The third node is disposed between the second current source and the switch circuit. The fourth node is disposed coupled with the second current source. The second circuit is configured for substantially equalizing voltages on the third node and the fourth node.
    Type: Grant
    Filed: May 21, 2014
    Date of Patent: August 16, 2016
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Steven Swei, Chih-Chang Lin, Tien-Chun Yang, Chan-Hong Chern, Ming-Chieh Huang