Patents by Inventor Chan-Hong Chern

Chan-Hong Chern has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220393041
    Abstract: The present disclosure provides a photo sensing device including a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, wherein the silicon layer includes a first doped region adjacent to a first side of the photosensitive member, wherein the first doped region has a first conductivity type, and a second doped region adjacent to a second side of the photosensitive member opposite to the first side, wherein the second doped region has a second conductivity type different from the first conductivity type, and a composite layer disposed between the photosensitive member and the silicon layer and surrounding the photosensitive member, and a portion of the composite layer proximal to the first doped region is doped with a dopant having the first conductivity type.
    Type: Application
    Filed: June 24, 2022
    Publication date: December 8, 2022
    Inventor: CHAN-HONG CHERN
  • Patent number: 11522526
    Abstract: Various embodiments of the present application are directed towards a level shifter with temperature compensation. In some embodiments, the level shifter comprises a transistor, a first resistor, and a second resistor. The first resistor is electrically coupled from a first source/drain of the transistor to a supply node, and the second resistor is electrically coupled from a second source/drain of the transistor to a reference node. Further, the first and second resistors have substantially the same temperature coefficients and comprise group III-V semiconductor material. By having both the first and second resistors, the output voltage of the level shifter is defined by the resistance ratio of the resistors. Further, since the first and second resistors have the same temperature coefficients, temperature induced changes in resistance is largely cancelled out in the ratio and the output voltage is less susceptible to temperature induced change than the first and second resistors individually.
    Type: Grant
    Filed: April 5, 2021
    Date of Patent: December 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Kun-Lung Chen
  • Publication number: 20220368326
    Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.
    Type: Application
    Filed: July 28, 2022
    Publication date: November 17, 2022
    Inventors: Chan-Hong Chern, Tysh-Bin Liu, Kun-Lung Chen
  • Publication number: 20220365378
    Abstract: An optical phase-shifting device includes a ribbed waveguide portion on an insulating layer, the waveguide portion having a p-n or p-i-n junction extending in a longitudinal direction and having a height. A pair of slab portions are disposed adjacent the waveguide portion, one on each side of the ribbed waveguide portion and on the insulation layer. The slab portion have higher doping concentrations than the respective doping concentrations in the ribbed waveguide portion. At least a portion of each slab portion has a height increasing with distance from the waveguide portion, with the slab height being smaller than that of the waveguide portion at the junction between the waveguide portion and slab portion. A pair of contact portions are formed adjacent the respective slab portion and further away from the waveguide portion. A portion of each contact portion can also have a height varying with distance from the waveguide portion.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 17, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chan-Hong Chern
  • Patent number: 11500151
    Abstract: A semiconductor arrangement is provided and includes a first dielectric layer over an optical device. A first metallization layer is over the first dielectric layer, and a first conductive line is in the first metallization layer. A first conductive via is in the first metallization layer and contacts the first conductive line. A second metallization layer is over the first metallization layer. A second conductive line is in the second metallization layer and contacts the first conductive via at a first interface. A heater is over the optical device and has a lowermost surface below the first interface and an uppermost surface above the first interface.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: November 15, 2022
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY LIMITED
    Inventor: Chan-Hong Chern
  • Publication number: 20220357518
    Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
    Type: Application
    Filed: July 26, 2022
    Publication date: November 10, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Chewn-Pu Jou, Chih-Tsung Shih, Feng-Wei Kuo, Lan-Chou Cho, Min-Hsiang Hsu, Weiwei Song
  • Publication number: 20220352399
    Abstract: A photodetector is provided. The photodetector includes a bottom electrode region in a semiconductor layer, a light absorption material in the semiconductor layer, and a first buffer layer sandwiched between a bottom surface of the light absorption material and the semiconductor layer. The first buffer layer includes, from bottom to top, a first Si layer, a first SiGe layer, a second Si layer, and a second SiGe layer. A first atomic percentage of Ge in the first SiGe layer is less than a second atomic percentage of Ge in the second SiGe layer. The photodetector further includes a top electrode region over the light absorption material.
    Type: Application
    Filed: July 14, 2022
    Publication date: November 3, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chan-Hong CHERN
  • Publication number: 20220352063
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.
    Type: Application
    Filed: July 13, 2022
    Publication date: November 3, 2022
    Inventors: Weiwei Song, Chan-Hong Chern, Feng-Wei Kuo, Lan-Chou Cho, Stefan Rusu
  • Publication number: 20220342239
    Abstract: A semiconductor device include: a first bus waveguide; a first silicon ring optically coupled to the first bus waveguide; a backup silicon ring optically coupled to the first bus waveguide; a first heater and a second heater configured to heat the first silicon ring and the backup silicon ring, respectively; and a first switch, where the first switch is configured to electrically couple the first silicon ring to a first radio frequency (RF) circuit when the first switch is at a first switching position, and is configured to electrically couple the backup silicon ring to the first RF circuit when the first switch is at a second switching position.
    Type: Application
    Filed: July 19, 2021
    Publication date: October 27, 2022
    Inventors: Weiwei Song, Stefan Rusu, Chan-Hong Chern, Chih-Chang Lin
  • Publication number: 20220336295
    Abstract: A manufacturing method of group III-V semiconductor package is provided. The manufacturing method includes the following steps. A wafer comprising group III-V semiconductor dies therein is provided. A chip probing (CP) process is performed to the wafer to determine reliabilities of the group III-V semiconductor dies, wherein the CP process comprises performing a multi-step breakdown voltage testing process to the group III-V semiconductor dies to obtain a first portion of dies of the group III-V semiconductor dies with breakdown voltages to be smaller than a predetermined breakdown voltage. A singulation process is performed to separate the group III-V semiconductor dies from the wafer. A package process is performed to form group III-V semiconductor packages including the group III-V semiconductor dies. A final testing process is performed on the group III-V semiconductor packages.
    Type: Application
    Filed: September 15, 2021
    Publication date: October 20, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yi-An Lai, Chan-Hong Chern, Chih-Hua Wang, Chu-Fu Chen, Kun-Lung Chen
  • Publication number: 20220328707
    Abstract: The present disclosure provides a photo sensing device, the photo sensing device includes a substrate, including a silicon layer at a front surface, a photosensitive member extending into and at least partially surrounded by the silicon layer, a first doped region having a first conductivity type at a first side of the photosensitive member, wherein the first doped region is in the silicon layer, and a second doped region having a second conductivity type different from the first conductivity type at a second side of the photosensitive member opposite to the first side, wherein the second doped region is in the silicon layer, and the first doped region is apart from the second doped region, and a superlattice layer disposed between the photosensitive member and the silicon layer, wherein the superlattice layer includes a first material and a second material different from the first material.
    Type: Application
    Filed: June 13, 2022
    Publication date: October 13, 2022
    Inventors: CHAN-HONG CHERN, WEIWEI SONG, CHIH-CHANG LIN, LAN-CHOU CHO, MIN-HSIANG HSU
  • Publication number: 20220308289
    Abstract: Integrated optical devices and methods of forming the same are disclosed. A method of forming an integrated optical device includes the following steps. A substrate is provided. The substrate includes, from bottom to top, a first semiconductor layer, an insulating layer and a second semiconductor layer. The second semiconductor layer is patterned to form a waveguide pattern. A surface smoothing treatment is performed to the waveguide pattern until a surface roughness Rz of the waveguide pattern is equal to or less than a desired value. A cladding layer is formed over the waveguide pattern.
    Type: Application
    Filed: June 16, 2022
    Publication date: September 29, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Min-Hsiang Hsu
  • Patent number: 11448828
    Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
    Type: Grant
    Filed: February 22, 2021
    Date of Patent: September 20, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Chewn-Pu Jou, Chih-Tsung Shih, Feng-Wei Kuo, Lan-Chou Cho, Min-Hsiang Hsu, Weiwei Song
  • Patent number: 11437990
    Abstract: Devices, systems, and methods are provided for generating a high, dynamic voltage boost. An integrated circuit (IC) includes a driving circuit having a first stage and a second stage. The driving circuit is configured to provide an overdrive voltage. The IC also includes a charge pump circuit coupled between the first stage and the second stage. The charge pump circuit is configured generate a dynamic voltage greater than the overdrive voltage. The IC also includes a bootstrap circuit coupled to the charge pump circuit, configured to further dynamically boost the overdrive voltage of the driving circuit.
    Type: Grant
    Filed: May 24, 2021
    Date of Patent: September 6, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company Limited
    Inventors: Chan-Hong Chern, Tysh-Bin Liu, Kun-Lung Chen
  • Publication number: 20220276453
    Abstract: Disclosed are apparatus and methods for optical coupling in optical communications. In one embodiment, an apparatus for optical coupling is disclosed. The apparatus includes: a planar layer; an array of scattering elements arranged in the planar layer at a plurality of intersections of a first set of concentric elliptical curves crossing with a second set of concentric elliptical curves rotated proximately 90 degrees to form a two-dimensional (2D) grating; a first taper structure formed in the planar layer connecting a first convex side of the 2D grating to a first waveguide; and a second taper structure formed in the planar layer connecting a second convex side of the 2D grating to a second waveguide. Each scattering element is a pillar into the planar layer. The pillar has a top surface whose shape is a concave polygon having at least 6 corners.
    Type: Application
    Filed: February 26, 2021
    Publication date: September 1, 2022
    Inventors: Chan-Hong CHERN, Min-Hsiang HSU
  • Patent number: 11428871
    Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device including a taper portion and a grating portion. The grating portion is connected to the taper portion. The grating portion includes grating patterns. Ends of the grating patterns are separated from an outer edge of the optical device by a distance.
    Type: Grant
    Filed: September 28, 2020
    Date of Patent: August 30, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventor: Chan-Hong Chern
  • Publication number: 20220269006
    Abstract: An optical device for coupling light propagating between a waveguide and an optical transmission component is provided. The optical device includes a taper portion and a grating portion. The taper portion is disposed between the grating portion and the waveguide. The grating portion includes rows of grating patterns. A first size of a first grating pattern in a first row of grating patterns is larger than a second size of a second grating pattern in a second row of grating patterns. A first distance between the first row of grating patterns and the waveguide is less than a second distance between the second row of grating patterns and the waveguide.
    Type: Application
    Filed: February 22, 2021
    Publication date: August 25, 2022
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chan-Hong Chern, Chih-Chang Lin, Chewn-Pu Jou, Chih-Tsung Shih, Feng-Wei Kuo, Lan-Chou Cho, Min-Hsiang Hsu, Weiwei Song
  • Publication number: 20220269000
    Abstract: A semiconductor arrangement is provided and includes a first dielectric layer over an optical device. A first metallization layer is over the first dielectric layer, and a first conductive line is in the first metallization layer. A first conductive via is in the first metallization layer and contacts the first conductive line. A second metallization layer is over the first metallization layer. A second conductive line is in the second metallization layer and contacts the first conductive via at a first interface. A heater is over the optical device and has a lowermost surface below the first interface and an uppermost surface above the first interface.
    Type: Application
    Filed: February 22, 2021
    Publication date: August 25, 2022
    Inventor: Chan-Hong CHERN
  • Publication number: 20220271015
    Abstract: Semiconductor package structures are provided. An interposer is bonded to a printed circuit board (PCB) or package substrate through first solder bumps disposed on a first side of the interposer. The first solder bumps have a first pitch. A plurality of semiconductor chips are formed, and each of the semiconductor chips is bonded to a second side of the interposer through second solder bumps. The second solder bumps have a second pitch that is less than the first pitch. Each of the semiconductor chips includes a substrate with one or more transistors or integrated circuits formed thereon.
    Type: Application
    Filed: February 25, 2022
    Publication date: August 25, 2022
    Inventors: Chan-Hong Chern, Mark Chen
  • Patent number: 11417596
    Abstract: In some embodiments, the present disclosure relates to an integrated chip that includes an insulator layer arranged over a substrate. Further, an upper routing structure is arranged over the insulator layer and is made of a semiconductor material. A lower optical routing structure is arranged below the substrate and is embedded in a lower dielectric structure. The integrated chip further includes an anti-reflective layer that is arranged below the substrate and directly contacts the substrate.
    Type: Grant
    Filed: August 4, 2020
    Date of Patent: August 16, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Weiwei Song, Chan-Hong Chern, Feng-Wei Kuo, Lan-Chou Cho, Stefan Rusu