Abstract: In an overlay measurement method, an overlay mark having programmed overlay values is provided. The overlay mark is scanned with an electron beam to obtain a voltage contrast image. A defect function that changes according to the overlay value is obtained from voltage contrast image data. Self-cross correlation is performed on the defect function to determine an overlay.

Abstract: A method of fabricating a semiconductor device includes forming a photoresist layer on a lower structure to have a first thickness, exposing a portion of the photoresist layer to form an exposed portion and a non-exposed portion of the photoresist layer, removing a part of the photoresist layer to form a photoresist layer having a second thickness that smaller than the first thickness, and removing the exposed portion or the non-exposed portion of the photoresist layer having the second thickness to form a photoresist pattern.

Abstract: A semiconductor device includes a first stack structure in a first region, a first channel structure in contact with the substrate, a second stack structure on the first stack structure, a second channel structure connected to the first channel structure, a third stack structure on the second stack structure, a third channel structure connected to the second channel structure, a first mold structure in a second region, first overlay structures on the first mold structure, a second mold structure on the first mold structure, second overlay structures on the second mold structure, a third mold structure on the second mold structure, and third overlay structures on the third mold structure, wherein the first to third overlay structures are on an overlay mark region, and the first to third overlay structures are in at least one of quadrants in the overlay mark region.

Abstract: Disclosed are methods of aligning a semiconductor wafer in a scanner device. In a method of aligning a semiconductor wafer in a scanner device, a first mark pair includes two marks among a plurality of marks of a semiconductor wafer. A plurality of mark pairs including the first mark pair are set by performing a geometric transformation at least once on the first mark pair. A plurality of coarse model parameters are generated by performing a coarse wafer alignment (COWA) based on each of the plurality of mark pairs. A fine model parameter is generated by performing a fine wafer alignment (FIWA) based on the plurality of marks. Whether an alignment of the semiconductor wafer is successful is determined based on the plurality of coarse model parameters and the fine model parameter. A subsequent process is performed based on a determination that the alignment of the semiconductor wafer is successful.

Abstract: The method including forming a first photoresist (PR) pattern by exposing first field areas of a first PR layer, forming a second PR pattern by exposing first top field areas and first bottom field areas of a second PR layer, measuring a first top intra-field overlay for the first top field areas and a first bottom intra-field overlay for the first bottom field areas, and determining a top intra-field correction parameter and a bottom intra-field correction parameter based on the first top intra-field overlay and the first bottom intra-field overlay, respectively, may be provided.

Abstract: Provided are an overlay correction method for effectively correcting an overlay due to degradation of a wafer table, and an exposure method and a semiconductor device manufacturing method, which include the overlay correction method, wherein the overlay correction method includes acquiring leveling data regarding a wafer, converting the leveling data into overlay data, splitting a shot into sub-shots via shot size split, extracting a model for each sub-shot from the overlay data, and correcting an overlay parameter of exposure equipment on the basis of the model for each sub-shot, wherein the correction of the overlay parameter is applied in real time to an exposure process for the wafer in a feedforward method.

Abstract: A method of determining an overlay reference wavelength, the method comprising: forming a pattern structure including a wafer and overlay keys on the wafer; obtaining first setup values of the pattern structure for first measurement wavelengths, respectively; selecting second measurement wavelengths among the first measurement wavelengths by filtering the first measurement wavelengths based on the first setup values; obtaining second setup values of the pattern structure for the second measurement wavelengths, respectively; and selecting a reference wavelength among the second measurement wavelengths based on the second setup values, wherein each of the first setup values is proportional to a deviation value of target sigma values of the overlay keys at a respective first measurement wavelength, and wherein each of the second setup values is inversely proportional to a deviation value of stack sensitivity values of the overlay keys at a respective second measurement wavelength.

Abstract: Provided is a method of forming patterns for a semiconductor device, the method comprising: forming an etching target film on a substrate; and forming a photoresist pattern on the etching target film, wherein the photoresist pattern includes a first exposure pattern on the etching target film and a second exposure pattern on the first exposure pattern, wherein forming the photoresist pattern comprises: forming a first photoresist film on the etching target film; forming the first exposure pattern by removing at least a portion of the first photoresist film through a first exposure process; forming a second photoresist film on the first exposure pattern; and forming the second exposure pattern by removing at least a portion of the second photoresist film through a second exposure process, wherein the photoresist pattern has a thickness that decreases from a central portion to an edge portion thereof.

Abstract: A substrate treatment method includes determining a first model of an upper substrate and a lower substrate based on alignment error data taken by measuring positions of a plurality of alignment marks of each of the upper substrate and the lower substrate, determining a second model of the upper substrate and the lower substrate based on first sampling alignment error data regarding at least one alignment mark from the alignment error data, determining a third model of the upper substrate and the lower substrate based on second sampling alignment error data taken by measuring positions of the at least one alignment mark, determining a fourth model by correcting the third model based on a difference between the second model and the first model, and aligning a position of a substrate selected between the upper substrate and the lower substrate according to the fourth model.

Abstract: A substrate treating method includes identifying correlation data between a height value of each of a plurality of reference substrates and a vacuum pressure applied to secure each of the plurality of reference substrates to a chuck, and determining, based on the correlation data and a height value of a substrate, a flow amount of a fluid discharged by a vacuum pump to produce a vacuum pressure applied to secure the substrate to the chuck.

Abstract: A method of manufacturing a semiconductor device includes forming a mask layer structure on a substrate including a first region and a second region, the mask layer structure covering the first region and the second region of the substrate, forming a first photoresist pattern covering at least part of the second region and exposing the first region of the mask layer structure, forming a second photoresist pattern on the mask layer structure and the first photoresist pattern, and etching the mask layer structure by using the first photoresist pattern and the second photoresist pattern.

Abstract: A method for fabricating a semiconductor device using an overlay measurement and a semiconductor device fabricated by the method are provided. The method includes forming a lower pattern including a lower overlay key pattern having a first pitch, on a substrate, forming an upper pattern including an upper overlay key pattern having a second pitch different from the first pitch, on the lower pattern, measuring an overlay between the lower overlay key pattern and the upper overlay key pattern, removing the upper overlay key pattern, and after removing the upper overlay key pattern, performing an etching process using the upper pattern as an etching mask.

Abstract: Provided is a system and method of manufacturing a semiconductor device. The method includes: dividing a wafer into a plurality of fields arranged in rows and columns; measuring an overlay error of a pattern in each of the plurality of fields and collecting overlay error data; and correcting the overlay error of the pattern in a first field among the plurality of fields, wherein the correcting the overlay error of the pattern in the first field includes: dividing the first field into first and second regions, wherein the overlay error of the second region is greater than an overlay error of the first region; comparing the overlay error of the first and second regions; defining a first weight for the first region and a second weight for the second region; obtaining a correction parameter by executing regression using the overlay error data; and providing the correction parameter to a scanner.

Abstract: A method of forming a pattern includes forming an etching target layer on a substrate, forming an under layer on the etching target layer, forming a first resist pattern on the under layer, forming a second resist layer covering a side wall and a top surface of the first resist pattern and extending on a top surface of the under layer, forming a second resist pattern covering the side wall of the first resist pattern by removing a portion of the second resist layer on the top surface of the under layer, and performing an etching process using a resist structure as an etch mask, where the resist structure includes the first resist pattern and the second resist pattern.

Abstract: Provided are a method of configuring an extreme ultraviolet (EUV) source capable of improving optical performance before an exposure process and an EUV exposure method using the EUV source. The method of configuring an EUV source includes generating an object spectrum map for a layout of a mask pattern, generating a pupil map corresponding to the object spectrum map, and configuring an EUV illumination mode by selecting mirrors in at least a portion of a first region of the pupil map in which a certain condition is satisfied, and applying perturbation of a pole balance to the plurality of mirrors.

Abstract: A semiconductor device manufacturing method includes determining whether or not a reticle writing correction needs to be applied to a mask for an exposure process, when determining that the reticle writing correction needs to be applied, manufacturing the mask to which the reticle writing correction is applied by using the mask to which the reticle writing correction is applied, measuring an overlay and performing a correction based on the basis of on the measured overlay, determining whether or not a value of the measured overlay is greater than a specification, and when the value of the measured overlay is not greater than the specification, performing a subsequent process.

Abstract: A substrate bonding apparatus for bonding a first substrate to a second substrate includes a lower bonding chuck configured to support the first substrate, an upper bonding chuck facing the lower bonding chuck and configured to support the second substrate, a gas discharge device provided through the center of the upper bonding chuck and configured to discharge pressurized gas to a top surface of the second substrate, a gas supply unit configured to supply the pressurized gas to the gas discharge device, and a controller configured to control the gas discharge device and the gas supply unit and the controller controls vertical movement of the gas discharge device with respect to the upper bonding chuck, and a flow rate and pressure of the pressurized gas in the gas discharge device.

Abstract: A method of determining an overlay reference wavelength, the method comprising: forming a pattern structure including a wafer and overlay keys on the wafer; obtaining first setup values of the pattern structure for first measurement wavelengths, respectively; selecting second measurement wavelengths among the first measurement wavelengths by filtering the first measurement wavelengths based on the first setup values; obtaining second setup values of the pattern structure for the second measurement wavelengths, respectively; and selecting a reference wavelength among the second measurement wavelengths based on the second setup values, wherein each of the first setup values is proportional to a deviation value of target sigma values of the overlay keys at a respective first measurement wavelength, and wherein each of the second setup values is inversely proportional to a deviation value of stack sensitivity values of the overlay keys at a respective second measurement wavelength.

Abstract: A method of manufacturing an integrated circuit (IC) device, the method including forming an underlayer on a feature layer such that the underlayer includes an acid generator; forming an acid-containing underlayer by generating a first acid from the acid generator; forming a photoresist film on the acid-containing underlayer; generating a second acid in a first area of the photoresist film by exposing the first area of the photoresist film; diffusing the first acid from the acid-containing underlayer into the first area of the photoresist film; and forming a photoresist pattern by developing the photoresist film.

Abstract: A method for manufacturing a semiconductor device includes providing a first pre-reticle including a first overlay mark and a first on-cell pattern. A second pre-reticle is provided that includes a second overlay mark and a second on-cell pattern. A first pattern is formed from the first pre-reticle using a first illumination system. A second pattern is formed from the second pre-reticle using a second illumination system. An overlay error is measured between the first pattern and the second pattern. A corrected reticle is formed based on the measured overlay error.