Abstract: A display device includes a pixel electrode; a pixel circuit connected to the pixel electrode; a repair line overlapping at least a part of the pixel circuit; and a shielding line overlapping at least a part of the repair line and connected to a constant power source.

Abstract: The method including forming a first photoresist (PR) pattern by exposing first field areas of a first PR layer, forming a second PR pattern by exposing first top field areas and first bottom field areas of a second PR layer, measuring a first top intra-field overlay for the first top field areas and a first bottom intra-field overlay for the first bottom field areas, and determining a top intra-field correction parameter and a bottom intra-field correction parameter based on the first top intra-field overlay and the first bottom intra-field overlay, respectively, may be provided.

Abstract: The present disclosure relates to a display device. According to an embodiment of the disclosure, a display device including a first pixel which includes a first gate node including a first vertical portion and a first horizontal portion, and a first pixel electrode, and a second pixel which includes a second gate node including a second vertical portion and a second horizontal portion, and a second pixel electrode, wherein at least a part of each of the first horizontal portion and the second horizontal portion is disposed between facing surfaces of the first pixel electrode and the second pixel electrode so as not to overlap the first and second pixel electrodes.

Abstract: A method for fabricating a semiconductor device using an overlay measurement and a semiconductor device fabricated by the method are provided. The method includes forming a lower pattern including a lower overlay key pattern having a first pitch, on a substrate, forming an upper pattern including an upper overlay key pattern having a second pitch different from the first pitch, on the lower pattern, measuring an overlay between the lower overlay key pattern and the upper overlay key pattern, removing the upper overlay key pattern, and after removing the upper overlay key pattern, performing an etching process using the upper pattern as an etching mask.

Abstract: A control box for charging includes a second connector disposed at a first end of the control box and configured to be coupled to a first connector provided at a first end of a supply cable configured to be connected to an external power source. The control box includes a retainer configured to prevent separation of the first connector when the first connector and the second connector are completely coupled. A top of the control box is open at a position corresponding to the second connector and the retainer is inserted through the open top and moved up and down.

Abstract: Provided are an overlay correction method for effectively correcting an overlay due to degradation of a wafer table, and an exposure method and a semiconductor device manufacturing method, which include the overlay correction method, wherein the overlay correction method includes acquiring leveling data regarding a wafer, converting the leveling data into overlay data, splitting a shot into sub-shots via shot size split, extracting a model for each sub-shot from the overlay data, and correcting an overlay parameter of exposure equipment on the basis of the model for each sub-shot, wherein the correction of the overlay parameter is applied in real time to an exposure process for the wafer in a feedforward method.

Abstract: A photolithography system includes a light source, a photomask stage, a projection optical system and a wafer stage, and the projection optical system includes an anamorphic lens. In a photolithography method, a wafer and a photomask are mounted on the wafer stage and the photomask stage, respectively, and a first exposure process is performed using the photomask to transfer layouts of patterns included in the photomask to a first half field of the wafer. A relative position of the photomask with respect to the wafer is changed, and a second exposure process is performed to transfer the layouts of the patterns included in the photomask to a second half field of the wafer.

Abstract: A method of manufacturing an extreme ultraviolet mask including preparing a preliminary layout, forming a plurality of preliminary target patterns by using a plurality of preliminary spacer patterns formed by using the preliminary layout, evaluating presence or absence of an abnormal target pattern among the plurality of preliminary target patterns, preparing a layout configured to form a plurality of spacer patterns by modifying the preliminary layout when the plurality of preliminary target patterns include the abnormal target pattern, and manufacturing an extreme ultraviolet mask with the layout to form a plurality of target patterns by using the plurality of spacer patterns, wherein, the plurality of preliminary spacer patterns extend in one direction.

Abstract: A method of controlling semiconductor process includes forming a plurality of sample overlay keys by irradiating a first dose of extreme ultraviolet (EUV) light to a first photoresist layer formed on at least one sample wafer; determining a sample correction parameter for correcting a sample overlay error measured from the plurality of sample overlay keys; updating the sample correction parameter based on a difference between the first dose and a second dose; forming a plurality of main overlay keys by irradiating a second dose of extreme ultraviolet light to a second photoresist layer formed on the sample wafer based on the updated sample correction parameter; determining the main correction parameter based on a main overlay error measured from the plurality of main overlay keys; and performing a photolithography process on a wafer different from the sample wafer based on the main correction parameter.

Abstract: A display device includes a display panel including pixels in one pixel column and a gate driver for sequentially providing scan signals to the pixels. Each of the pixels includes a light emitting element, a first transistor for controlling a current amount of driving current flowing through the light emitting element and a second transistor for transferring a data signal to a gate electrode of the first transistor in response to a corresponding scan signal among the scan signals. A first pixel among the pixels is electrically connected to a first data line, and a second pixel adjacent to the first pixel among the pixels is electrically connected to a second data line different from the first data line. A second scan signal provided to the second pixel partially overlaps with a first scan signal provided to the first pixel.

Abstract: Provided are a method of selecting multi-wavelengths for overlay measurement, for accurately measuring overlay, and an overlay measurement method and a semiconductor device manufacturing method using the multi-wavelengths. The method of selecting multi-wavelengths for overlay measurement includes measuring an overlay at multiple positions on a wafer at each of a plurality of wavelengths within a set first wavelength range, selecting representative wavelengths that simulate the overlay of the plurality of wavelengths, from among the plurality of wavelengths, and allocating weights to the representative wavelengths, respectively.

Abstract: In an overlay measurement method, an overlay mark having programmed overlay values is provided. The overlay mark is scanned with an electron beam to obtain a voltage contrast image. A defect function that changes according to the overlay value is obtained from voltage contrast image data. Self-cross correlation is performed on the defect function to determine an overlay.

Abstract: An operating method of an extreme ultraviolet (EUV) lithography device includes defining a target image to render an illumination system, assigning priorities to respective positions of facets of a pupil facet mirror corresponding to the target image, assigning a mirror according to the assigned priorities using linear programming, generating the illumination system by selecting one of the facets of the pupil facet mirror based on a symmetry criterion, and converting mirror assignment information and source map information corresponding to the selected facet into a form recognizable by an EUV scanner.

Abstract: A semiconductor device includes first lower nanosheets; an upper isolation layer on the first lower nanosheets; first upper nanosheets on the upper isolation layer; a first upper source/drain region on the first upper nanosheets; a second upper source/drain region on the first upper nanosheets; a first gate electrode surrounding the first lower nanosheets, the upper isolation layer, and the first upper nanosheets; a first gate cut on a side of the first gate electrode and extending from a lower surface of the first gate electrode to an upper surface of the first gate electrode; a first through via inside the first gate cut and insulated from the first gate electrode; a first upper source/drain contact on and electrically connected to the first upper source/drain region; and a second upper source/drain contact on the first upper source/drain region and electrically connecting the second upper source/drain region with the first through via.

Abstract: A method of fabricating a semiconductor device may implement a desired mask pattern even without additionally performing an exposure process on any one of different regions of a substrate by forming a plurality of line patterns disposed at different intervals on the different regions, respectively, and applying a double patterning process to the plurality of line patterns. Such a method may increase product reliability and manufacturing economic feasibility of a semiconductor device.

Abstract: A display device includes a pixel. The pixel is electrically connected to a first power line, a second power line, and a data line. The pixel includes a first transistor, and a capacitor electrically connected between a gate electrode of the first transistor and an electrode of the first transistor. In a plan view, the data line extends in a second direction. The first power line extends in a first direction intersecting the second direction and overlaps the data line and the gate electrode of the first transistor. The second power line extends in the second direction, overlaps the data line, and overlaps the gate electrode of the first transistor.

Abstract: An overlay correcting method capable of optimizing correction of an overlay within a scanner correction limit of a scanner of a scanner system, and a photolithography method, a semiconductor device manufacturing method and the scanner system which are based on the overlay correcting method are provided. The overlay correcting method includes collecting overlay data by measuring an overlay of a pattern; calculating correction parameters of the overlay by performing regularized regression using the overlay data, the regularized regression being based on a correction limit of the scanner such that the correction parameters fall within the correction limit of the scanner; and providing the correction parameters to the scanner.

Abstract: A method for forming a resist pattern is disclosed. According to the method, a photosensitive layer is formed on a substrate by using an inorganic photoresist. The photosensitive layer is irradiated with a deep ultraviolet (DUV) light. The photosensitive layer is irradiated with an extreme ultraviolet (EUV) light after the irradiation of the DUV light. The photosensitive layer exposed to the EUV light is heated. The heated photosensitive layer is developed.

Abstract: A reflective mask used in an EUV exposure process includes a mask substrate, a reflective layer on the mask substrate, and an absorption layer on the reflective layer. The reflective mask includes a main region, an out-of-band region surrounding the main region, and an alignment mark region outside a periphery of the out-of-band region. The absorption layer in the alignment mark region includes an alignment mark and an anti-reflection pattern adjacent the alignment mark, and the anti-reflection pattern includes line-and-space patterns having a predetermined line width in the alignment mark region.

Abstract: A method of fabricating a semiconductor device includes forming a photoresist layer on a lower structure to have a first thickness, exposing a portion of the photoresist layer to form an exposed portion and a non-exposed portion of the photoresist layer, removing a part of the photoresist layer to form a photoresist layer having a second thickness that smaller than the first thickness, and removing the exposed portion or the non-exposed portion of the photoresist layer having the second thickness to form a photoresist pattern.