Abstract: A method, of training an anomaly detecting model using a plurality of pieces of graph data, includes: (a) inputting one piece of graph data that has not yet been input, among the plurality of pieces of graph data, to a graph neural network (GNN) AutoEncoder calculating a probability of each edge as input data; (b) calculating a difference value (hereinafter, “edge difference value”) between an edge probability value of reconstructed data output by the GNN AutoEncoder and an edge value of the input data; (c) calculating an average value (hereinafter, “positive edge loss”) of a positive edge and an average value (hereinafter, “negative edge loss”) of a negative edge using the edge difference value, and calculating an edge prediction loss value of the reconstructed data by summing the positive edge loss and the negative edge loss; (d) retraining the GNN AutoEncoder until the edge prediction loss value is minimized.

Abstract: A gate oxide layer for a high voltage transistor is formed using methods that avoid thinning in the corners of the gate oxide layer. A recess is formed in a silicon substrate. The exposed surfaces of the recess are thermally oxidized to form a thermal oxide layer of the gate oxide layer. A high temperature oxide layer of the gate oxide layer is then formed within the exposed surfaces of the recess by chemical vapor deposition. The combination of the thermal oxide layer and the high temperature oxide layer results in a gate oxide layer that does not exhibit the double hump phenomenon in the drain current vs. gate voltage curve. The high temperature oxide layer may include a rim that extends out of the recess.

Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

Abstract: This disclosure is directed to a circuit that includes a substrate, a target device on the substrate, and an electrostatic discharge (ESD) device electrically coupled to the target device. The ESD device includes an ESD detection circuit electrically coupled to a first reference voltage supply and a second reference voltage supply, an inverter circuit electrically coupled to the ESD detection circuit and configured to trigger in response to an ESD event on the first or second reference voltage supply, a rectifier circuit electrically coupled to the inverter circuit and configured to rectify a current discharged from the inverter circuit, and a transistor electrically coupled to the rectifier circuit and configured to discharge a remaining current passing through the rectifier circuit.

Abstract: An aberration in a fetal genome can be identified by analyzing a sample of fetal and maternal DNA. Classifications of whether an aberration (amplification or deletion) exists in a subchromosomal region are determined using count-based and size-based methods. The count classification and the size classification can be used in combination to determine whether only the fetus or only the mother, or both, have the aberration in the subchromosomal region, thereby avoiding false positives when the mother has the aberration and the fetus does not.

Abstract: Disclosed is an optical phased array antenna for a lidar that outputs output light provided from a light source to a measurement object and that receives reflective light reflecting from the measurement object, the optical phased array antenna including: a combiner configured to receive output light output from the light source or to output the reflective light; a phase modulation module configured to modulate a phase of the output light input from the combiner or the reflective light that is transmitted to the combiner; and an optical input/output unit configured to output the output light modulated by the phase modulation module or receive the reflective light reflecting from the measurement object and configured to have an antenna element waveguide to which the output light or the reflective light propagates and that extends a predetermined length.

Abstract: A semiconductor device includes: a substrate; a seed layer disposed on the substrate; a compound semiconductor stack layer disposed on the seed layer; and a source metal layer and a drain metal layer disposed on the compound semiconductor stack layer. The semiconductor device further includes a conductive layer at least partially covering the source metal layer and the drain metal layer, and covering opposing side surfaces of the seed layer and opposing side surfaces of the compound semiconductor stack layer. The conductive layer electrically connects the seed layer and the source metal layer.

Abstract: A high voltage transistor may include a plurality of source/drain regions, a gate structure, and a gate oxide layer that enables the gate structure to selectively control a channel region between the source/drain regions. The gate oxide layer may extend laterally outward toward one or more of the plurality of source/drain regions such that at least a portion of the gate oxide layer is not under the gate structure. The gate oxide layer extending laterally outward from under the gate structure enables the gate oxide layer to be used as a self-aligned structure for forming the source/drain regions of the high voltage transistor. In particular, the gate oxide layer extending laterally outward from under the gate structure enables the gate oxide layer to be used to form the source/drain regions at a greater spacing from the gate structure without the use of additional implant masks when forming the source/drain regions.

Abstract: A built-in antenna includes a first printed circuit board (PCB) having antenna areas arranged so that at least one antenna area is arranged at each of the corners of the first PCB. The antenna areas are spaced apart from one another, and circuit components are arranged in areas other than the antenna areas. A second PCB has first antenna patterns respectively arranged at locations corresponding to the antenna areas on the first PCB. A third PCB is vertically coupled to the first and second PCBs to electrically connect them. The second PCB includes a second antenna pattern arranged in an area other than areas in which the first antenna patterns are arranged. This increases a degree of freedom in design and improves bandwidth and efficiency by arranging each antenna in a plate-shaped structure.

Abstract: The present disclosure describes a structure with a conductive plate and a method for forming the structure. The structure includes a gate structure disposed on a diffusion region of a substrate, a protective layer in contact with the diffusion region and covering a sidewall of the gate structure and a portion of a top surface of the gate structure, and a first insulating layer in contact with the gate structure and the protective layer. The structure further includes a conductive plate in contact with the first insulating layer, where a first portion of the conductive plate laterally extends over a horizontal portion of the protective layer, and where a second portion of the conductive plate extends over a sidewall portion of the protective layer covering the sidewall of the gate structure. The structure further includes a second insulating layer in contact with the conductive plate.

Abstract: Some embodiments relate to an integrated circuit including a semiconductor substrate. A silicide structure is disposed over the semiconductor substrate in a cross-sectional view. A dielectric structure is in direct contact with an upper surface of the silicide structure in the cross-sectional view. A metal structure is in direct contact with an upper surface of the dielectric layer in the cross-sectional view, such that the silicide structure and the metal structure establish a bottom electrode and a top electrode, respectively, which are spaced apart from one another by the dielectric structure to establish a metal-insulator-silicide capacitor over the semiconductor substrate.

Abstract: An electronic package and a substrate structure thereof are provided, in which a circuit layer and a filling layer are formed on a substrate body in the substrate structure, where the circuit layer has a plurality of conductive traces separated from each other, so that the filling layer is filled between the plurality of conductive traces, and a portion of a surface of the circuit layer and a surface of the filling layer are covered with an insulating protective layer. Therefore, the insulating protective layer is carried by the filling layer, so that the insulating protective layer can be thin, thereby preventing the phenomenon of copper migration from occurring to the substrate structure in subsequent processes.

Abstract: An electronic package, a packaging substrate and a fabricating method are provided, in which a conductive bump pad is formed on an electrical contact pad of the packaging substrate, so that when an electronic element is bonded to the packaging substrate via a solder material in a flip-chip process, the conductive bump pad can guide the flow of the solder material. Therefore, the problem of empty soldering caused by the solder material not effectively contacting with the electrical contact pad can be avoided.

Abstract: A shoe management includes an inner cabinet; a suction port; a discharge port; a connection flow path; a dehumidifying agent; a heater; a sump; a recycling flow path; and a condenser. The air in the inner cabinet circulates in the shoe management apparatus while flowing in the connection flow path through the suction port, being dehumidified by the dehumidifying agent, and then, being discharged into the inner cabinet again through the discharge port. The heater is located in the connection flow path and recycles the dehumidifying agent. The condenser is located to be lower than the dehumidifying agent and higher than the sump, and is formed to be metallic.

Abstract: A shoe care apparatus includes an inner cabinet, an inlet, an outlet, a connection passage, a heater, a blower, and a desiccant block. The air inside the inner cabinet flows into the connection passage through the inlet, and is discharged back into the inner cabinet through the outlet after being dehumidified by the desiccant block while circulating inside the shoe care apparatus. The heater is located in the inner space of the desiccant block to recycle the desiccant of the desiccant block.

Abstract: A Schottky diode includes a substrate, a first drift region in the substrate, a second drift region in the substrate, a first dielectric layer disposed over the substrate, a first doped region in the first drift region, a second doped region in the second drift region, a third doped region in the first drift region, and a metal field plate disposed over the first dielectric layer. The first drift region and the first doped region include a first conductivity type. The second drift region, the second doped region and third doped region include a second conductivity type complementary to the first conductivity type. The first dielectric layer overlaps a portion of the first drift region and a portion of the second drift region. The second doped region is separated from the first doped region.

Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction substantially perpendicular to the first direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and each of the gate structures extending at least unilaterally substantially beyond a first side of the corresponding first or second active region that is proximal to the gap or a second side of the corresponding first or second active region that is distal to the gap; and some but not all of the gate structures also extending bilaterally substantially beyond each of the first and second sides of the corresponding first or second active region.

Abstract: A semiconductor structure is provided. The semiconductor structure includes a substrate, a deep trench isolation (DTI), an interconnect structure, and a conductive pillar. The DTI is disposed in the substrate and the interconnect structure is disposed over the substrate. The conductive pillar extends from the interconnect structure toward the substrate and penetrates the DTI. A method of manufacturing the semiconductor structure is also provided.

Abstract: A semiconductor device includes: first and second active regions extending in a first direction and separated by a gap relative to a second direction; and gate structures correspondingly over the first and second active regions, the gate structures extending in the second direction; and for each active region, a portion of each of some but not all of the gate structures (gate extension) extending partially into the gap; and when viewing the gate structures as a group, the group having a notched profile relative to the second direction, where notches in the notched profile correspond to ones of the gate structures which are substantially free of extending into the gap.

Abstract: A semiconductor structure includes first and second active regions extending in a first direction. The semiconductor structure further includes gate electrodes extending in a second direction perpendicular to the first direction. Each of the gate electrodes includes a first segment over at least one of the first active region or the second active region; a gate extension extending beyond each of the first active region and the second active region, wherein the gate extension has a uniform width in the first direction, and a conductive element, wherein a width of the conductive element in the first direction increases as a distance from the gate extension increases along an entirety of the conductive element in the second direction.