Patents by Inventor Chandra Joshi

Chandra Joshi has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 5954815
    Abstract: A computing system that contains an apparatus comprising an instruction memory to store a plurality of lines of a plurality of instructions, and a branch memory to store a plurality of branch prediction entries, each branch prediction entry containing information for predicting whether a branch designated by a branch instruction stored in the instruction memory will be taken when the branch instruction is executed. Each branch prediction entry includes a branch target field for indicating a target address of a line containing a target instruction to be executed if the branch is taken, a destination field indicating where the target instruction is located within the line indicated by the branch target address, and a source field indicating where the branch instruction is located within the line corresponding to the target address.
    Type: Grant
    Filed: January 10, 1997
    Date of Patent: September 21, 1999
    Assignee: Silicon Graphics, Inc.
    Inventors: Chandra Joshi, Paul Rodman, Peter Hsu, Monica R. Nofal
  • Patent number: 5604909
    Abstract: A computing system has first and second instruction storing circuits, each instruction storing circuit storing N instructions for parallel output. An instruction dispatch circuit, coupled to the first instruction storing circuit dispatches L instructions stored in the first instruction storing circuit, wherein L is less than or equal to N. An instruction loading circuit, coupled to the instruction dispatch circuit and to the first and second instruction storing circuits, loads L instructions from the second instruction storing circuit into the first instruction storing circuit after the L instructions are dispatched from the first instruction storing circuit and before further instructions are dispatched from the first instruction storing circuit. A bypass circuit for bypassing the second instruction storing circuit is also provided.
    Type: Grant
    Filed: December 15, 1993
    Date of Patent: February 18, 1997
    Assignee: Silicon Graphics Computer Systems, Inc.
    Inventors: Chandra Joshi, Paul Rodman, Peter Hsu, Monica R. Nofal
  • Patent number: 4069498
    Abstract: Heat is removed from the silicon devices in an integrated circuit package by means of a stud which is slidably mounted in a cap enclosing the integrated circuit device. A low melt solder is used to join the stud to the cap and the same solder is also deposited on the stud tip, which will subsequently contact the integrated circuit device in the package. After the integrated circuit, substrate and cap are assembled and sealed, the assembly is heated to melt the low melt solder so that the stud slides down and makes contact with the integrated circuit device. A controlled pressure can be applied to the stud if sliding does not occur. Thereafter, the assembly is allowed to cool. Upon cooling, a submicron gap exists between the solder on the tip of the stud and the device providing electrical isolation, but not significantly degrading the thermal path between the device and the ambient atmosphere.
    Type: Grant
    Filed: November 3, 1976
    Date of Patent: January 17, 1978
    Assignee: International Business Machines Corporation
    Inventor: Kailash Chandra Joshi