Abstract: A method is provided for fabricating a high quantum efficiency silicon (Si) nanoparticle embedded SiOXNY film for luminescence (electroluminescence—EL and photoluminescence—PL) applications. The method provides a bottom electrode, and deposits a Si nanoparticle embedded non-stoichiometric SiOXNY film, where (X+Y<2 and Y>0), overlying the bottom electrode. The Si nanoparticle embedded SiOXNY film is annealed. The annealed Si nanoparticle embedded SiOXNY film has an extinction coefficient (k) of less than about 0.001 as measured at 632 nanometers (nm), and a PL quantum efficiency (PLQE) of greater than 20%.

Abstract: A method is provided for forming a silicon (Si) nanocrystal embedded Si oxide electroluminescence (EL) device with a mid-bandgap transition layer. The method provides a highly doped Si bottom electrode, and forms a mid-bandgap electrically insulating dielectric film overlying the electrode. A Si nanocrystal embedded SiOx film layer is formed overlying the mid-bandgap electrically insulating dielectric film, where X is less than 2, and a transparent top electrode overlies the Si nanocrystal embedded SiOx film layer. The bandgap of the mid-bandgap dielectric film is about half that of the bandgap of the Si nanocrystal embedded SiOx film. In one aspect, the Si nanocrystal embedded SiOx film has a bandgap (Eg) of about 10 electronvolts (eV) and mid-bandgap electrically insulating dielectric film has a bandgap of about 5 eV. By dividing the high-energy tunneling processes into two lower energy tunneling steps, potential damage due to high power hot electrons is reduced.

Abstract: A high-density plasma hydrogenation method is provided. Generally, the method comprises: forming a silicon (Si)/oxide stack layer; plasma oxidizing the Si/oxide stack at a temperature of less than 400° C., using a high density plasma source, such as an inductively coupled plasma (ICP) source; introducing an atmosphere including H2 at a system pressure up to 500 milliTorr; hydrogenating the stack at a temperature of less than 400 degrees C., using the high density plasma source; and forming an electrode overlying the oxide. The electrode may be formed either before or after the hydrogenation. The Si/oxide stack may be formed in a number of ways. In one aspect, a Si layer is formed, and the silicon layer is plasma oxidized at a temperature of less than 400 degrees C., using an ICP source. The oxide formation, additional oxidation, and hydrogenation steps can be conducted in-situ in a common chamber.

Abstract: A non-stoichiometric SiOXNY thin-film optical filter is provided. The filter is formed from a substrate and a first non-stoichiometric SiOX1NY1 thin-film overlying the substrate, where (X1+Y1<2 and Y1>0). The first non-stoichiometric SiOX1NY1 thin-film has a refractive index (n1) in the range of about 1.46 to 3, and complex refractive index (N1=n1+ik1), where k1 is an extinction coefficient in a range of about 0 to 0.5. The first non-stoichiometric SiOX1NY1 thin-film may be either intrinsic or doped. In one aspect, the first non-stoichiometric SiOX1NY1 thin-film has nanoparticles with a size in the range of about 1 to 10 nm. A second non-stoichiometric SiOX2NY2 thin-film may overlie the first non-stoichiometric SiOX1NY1 thin-film, where Y1?Y2. The second non-stoichiometric SiOX1NY1 thin-film may be intrinsic and doped. In another variation, a stoichiometric SiOX2NY2 thin-film, intrinsic or doped, overlies the first non-stoichiometric SiOX1NY1 thin-film.

Abstract: A method of fabricating a grayscale reticule includes preparing a quartz substrate; depositing a layer of silicon-rich oxide on the quartz substrate; depositing a layer of silicon nitride as an oxidation barrier layer on the silicon-rich oxide layer; depositing and patterning a layer of photoresist; etching the silicon nitride layer with a pattern for the silicon nitride layer; removing the photoresist; cleaning the quartz substrate and the remaining layers; oxidizing the quartz substrate and the layers thereon, thereby converting the silicon-rich oxide layer to a transparent silicon dioxide layer; removing the remaining silicon nitride layer; forming the quartz substrate and the silicon dioxide thereon into a reticule; and using the reticule to pattern a microlens array.

Abstract: A light emitting device using a silicon (Si) nanocrystalline Si insulating film is presented with an associated fabrication method. The method provides a doped semiconductor or metal bottom electrode. Using a high density plasma-enhanced chemical vapor deposition (HDPECVD) process, a Si insulator film is deposited overlying the semiconductor electrode, having a thickness in a range of 30 to 200 nanometers (nm). For example, the film may be SiOx, where X is less than 2, Si3Nx, where X is less than 4, or SiCx, where X is less than 1. The Si insulating film is annealed, and as a result, Si nanocrystals are formed in the film. Then, a transparent metal electrode is formed overlying the Si insulator film. An annealed Si nanocrystalline SiOx film has a turn-on voltage of less than 20 volts, as defined with respect to a surface emission power of greater than 0.03 watt per square meter.

Abstract: A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the gate insulator at a temperature of less than 400° C., using a high-density plasma source; forming a first source/drain region overlying the gate top surface; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source/drain regions. When the silicon oxide thin-film gate insulator is deposited overlying the gate a Si oxide layer, a low temperature deposition process can be used, so that a step-coverage of greater than 65% can be obtained.

Abstract: A method is provided for forming a low-temperature vertical gate insulator in a vertical thin-film transistor (V-TFT) fabrication process. The method comprises: forming a gate, having vertical sidewalls and a top surface, overlying a substrate insulation layer; depositing a silicon oxide thin-film gate insulator overlying the gate; plasma oxidizing the gate insulator at a temperature of less than 400° C., using a high-density plasma source; forming a first source/drain region overlying the gate top surface; forming a second source/drain region overlying the substrate insulation layer, adjacent a first gate sidewall; and, forming a channel region overlying the first gate sidewall, in the gate insulator interposed between the first and second source/drain regions. When the silicon oxide thin-film gate insulator is deposited overlying the gate a Si oxide layer, a low temperature deposition process can be used, so that a step-coverage of greater than 65% can be obtained.

Abstract: A method of fabricating a grayscale reticle includes preparing a quartz substrate; depositing a layer of silicon-rich oxide on the quartz substrate; depositing a layer of silicon nitride as an oxidation barrier layer on the silicon-rich oxide layer; depositing and patterning a layer of photoresist; etching the silicon nitride layer with a pattern for the silicon nitride layer; removing the photoresist; cleaning the quartz substrate and the remaining layers; oxidizing the quartz substrate and the layers thereon, thereby converting the silicon-rich oxide layer to a transparent silicon dioxide layer; removing the remaining silicon nitride layer; forming the quartz substrate and the silicon dioxide thereon into a reticle; and using the reticle to pattern a microlens array.

Abstract: A pixel-by-pixel digitally-addressable, pixelated, fluid-assay, active-matrix micro-structure including plural pixels formed preferably on a glass or plastic substrate, wherein each pixel, formed utilizing low-temperature TFT and Si technology, includes (a) at least one functionalized, digitally-addressable assay sensor including at least one functionalized, digitally-addressable assay site which has been affinity-functionalized to respond to a selected, specific fluid-assay material, and (b) disposed operatively adjacent that sensor and its associated assay site, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the sensor and its associated assay site, a selected, ambient, electromagnetic field environment which is structured to assist, selectively and optionally only, in the reading-out of an assay-result response from the assay sensor and assay site.

Abstract: A method of performing a fluid-material assay employing a device including at least one active pixel having a sensor with an assay site functionalized for selected fluid-assay material. The method includes exposing the pixel's sensor assay site to such material, and in conjunction with such exposing, and employing the active nature of the pixel, remotely requesting from the pixel's sensor assay site an assay-result output report. The method further includes, in relation to the employing step, creating, relative to the sensor's assay site in the at least one pixel, a predetermined, pixel-specific electromagnetic field environment.

Abstract: A method of producing a precursor, active-matrix, fluid-assay micro-structure including the steps of (1) utilizing low-temperature TFT and Si technology, establishing preferably on a glass or plastic substrate a matrix array of non-functionalized pixels, and (2) preparing at least one of these pixels for individual, digitally-addressed (a) functionalization, and (b) reading out, ultimately, of completed assay results.

Abstract: A method for producing an active-matrix, fluid-assay micro-structure including, utilizing low-temperature TFT and Si technology, establishing preferably on a glass or plastic substrate a matrix array of digitally-addressable, assay-material-specific-functionalizable pixels, and employing pixel-specific digital addressing for selected, array-established pixels, individually functionalizing these pixels.

Abstract: A digitally-addressable, pixelated, DNA fluid-assay, active-matrix micro-structure formed, utilizing low-temperature TFT and Si technology, on a substrate preferably made of glass or plastic, and including at least one pixel which is defined by (a) an addressable pixel site, (b) a sensor home structure disposed within that site for receiving and hosting a functionalized assay site possessing a DNA oligonucleotide probe, and (c) an addressable, pixel-site-specific, energy-field-producing functionalizer (preferably optical) operable to functionalize such a probe on the assay site. Each pixel may also include a pixel-integrated optical detector. Further disclosed are related methodology facets involving (1) the making of such a micro-structure (a) in a precursor form (without a functionalized probe), and thereafter (b) in a finalized/functionalized form (with such a probe), and (2) the ultimate use of a completed micro-structure in the performance of a DNA assay.

Abstract: A pixel-by-pixel, digitally-addressable, pixelated, precursor, fluid-assay, active-matrix micro-structure including plural pixels formed preferably on a glass or plastic substrate, wherein each pixel, formed utilizing low-temperature TFT and Si technology, includes (a) at least one non-functionalized, digitally-addressable assay sensor, and (b), disposed operatively adjacent this sensor, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the at least one assay sensor, an ambient electromagnetic field environment which is structured to assist in functionalizing, as a possession on said at least one assay sensor, at least one digitally-addressable assay site which will display an affinity for a selected fluid-assay material.

Abstract: A pixel-by-pixel, digitally-addressable, pixelated, precursor, fluid-assay, active-matrix micro-structure including plural pixels formed on a substrate, wherein each pixel includes (a) at least one non-functionalized, digitally-addressable assay sensor, and (b), disposed operatively adjacent this sensor, digitally-addressable and energizable electromagnetic field-creating structure which is selectively energizable to create, in the vicinity of the at least one assay sensor, an ambient electromagnetic field environment which is structured to assist in functionalizing, as a possession on said at least one assay sensor, at least one digitally-addressable assay site which will display an affinity for a selected fluid-assay material.

Abstract: A method for forming a high-luminescence Si electroluminescence (EL) phosphor is provided, with an EL device made from the Si phosphor. The method comprises: depositing a silicon-rich oxide (SRO) film, with Si nanocrystals, having a refractive index in the range of 1.5 to 2.1, and a porosity in the range of 5 to 20%; and, post-annealing the SRO film in an oxygen atmosphere. DC-sputtering or PECVD processes can be used to deposit the SRO film. In one aspect the method further comprises: HF buffered oxide etching (BOE) the SRO film; and, re-oxidizing the SRO film, to form a SiO2 layer around the Si nanocrystals in the SRO film. In one aspect, the SRO film is re-oxidized by annealing in an oxygen atmosphere. In this manner, a layer of SiO2 is formed around the Si nanocrystals having a thickness in the range of 1 to 5 nanometers (nm).

Abstract: An oxide interface and a method for fabricating an oxide interface are provided. The method comprises forming a silicon layer and an oxide layer overlying the silicon layer. The oxide layer is formed at a temperature of less than 400° C. using an inductively coupled plasma source. In some aspects of the method, the oxide layer is more than 20 nanometers (nm) thick and has a refractive index between 1.45 and 1.47. In some aspects of the method, the oxide layer is formed by plasma oxidizing the silicon layer, producing plasma oxide at a rate of up to approximately 4.4 nm per minute (after one minute). In some aspects of the method, a high-density plasma enhanced chemical vapor deposition (HD-PECVD) process is used to form the oxide layer. In some aspects of the method, the silicon and oxide layers are incorporated into a thin film transistor.

Abstract: A method is provided for forming a Si and Si—Ge thin films. The method comprises: providing a low temperature substrate material of plastic or glass; supplying an atmosphere; performing a high-density (HD) plasma process, such as an HD PECVD process using an inductively coupled plasma (ICP) source; maintaining a substrate temperature of 400 degrees C., or less; and, forming a semiconductor layer overlying the substrate that is made from Si or Si-germanium. The HD PECVD process is capable of depositing Si at a rate of greater than 100 ? per minute. The substrate temperature can be as low as 50 degrees C. Microcrystalline Si, a-Si, or a polycrystalline Si layer can be formed over the substrate. Further, the deposited Si can be either intrinsic or doped. Typically, the supplied atmosphere includes Si and H. For example, an atmosphere can be supplied including SiH4 and H2, or comprising H2 and Silane with H2/Silane ratio in the range of 0–100.

Abstract: Methods are provided for forming silicon dioxide (SiO2) on a silicon carbide (SiC) substrate. The method comprises: providing a SiC substrate; supplying an atmosphere including oxygen; performing a high-density (HD) plasma-based process; and, forming a SiO2 layer overlying the SiC substrate. Typically, performing the HD plasma-based process includes connecting a top electrode to an inductively coupled HD plasma source. In one aspect, SiO2 is grown on the SiC substrate. Then, an HD plasma oxidation process is performed that creates a reactive oxygen species and breaks the Si—C bonds in the SiC substrate, to form free Si and C atoms in the SiC substrate. The free Si atoms in the SiC substrate are bonded to the HD plasma-generated reactive oxygen species, and the SiO2 layer is grown.