Patents by Inventor Chandra Mouli

Chandra Mouli has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10607988
    Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.
    Type: Grant
    Filed: April 30, 2019
    Date of Patent: March 31, 2020
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Srinivas Pulugurtha, Rajesh N. Gupta
  • Publication number: 20200085019
    Abstract: Systems, methods, and apparatuses for performing analytics for equine-related conditions from fetlock sensors include receiving sensor data from one or more sensors attached to one or more fetlock wearable devices. Each of the one or more fetlock wearable devices are configured to attach to a fetlock of a respective limb of a horse. The analytics system compares the sensor data to one or more baseline measurement values. The analytics system detects a condition responsive to comparing the sensor data to one or more baseline measurement values. The analytics system transmits an alert to one or more remote devices responsive to detecting the condition.
    Type: Application
    Filed: September 18, 2019
    Publication date: March 19, 2020
    Applicant: HORSEPOWER TECHNOLOGIES, INC.
    Inventors: David Wayne Gilbert, Chandra Mouli Ramani, Victoria Brougham Thompson
  • Publication number: 20200066617
    Abstract: Apparatuses and methods ate disclosed herein for the formation of to capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate. Wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.
    Type: Application
    Filed: October 30, 2019
    Publication date: February 27, 2020
    Applicant: MICRON TECHNOLOGY, INC.
    Inventors: DEEPAK C. PANDEY, HAITAO LIU, CHANDRA MOULI
  • Patent number: 10568112
    Abstract: A device may include one or more processors to receive priority information corresponding to a virtual machine of a computing environment, receive a packet associated with the virtual machine, determine a priority associated with the virtual machine based on the priority information, the priority information indicating the priority associated with the virtual machine relative to other virtual machines of the computing environment, and/or assign the packet to a queue associated with a service node of the computing environment based on the virtual machine, the packet to be output from the queue based on the priority associated with the virtual machine.
    Type: Grant
    Filed: September 11, 2017
    Date of Patent: February 18, 2020
    Assignee: Juniper Networks, Inc.
    Inventors: Avinash Kumar Singh, Chandra Mouli
  • Patent number: 10535711
    Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
    Type: Grant
    Filed: October 24, 2017
    Date of Patent: January 14, 2020
    Assignee: Micron Technology, Inc.
    Inventor: Chandra Mouli
  • Publication number: 20190371816
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.
    Type: Application
    Filed: August 14, 2019
    Publication date: December 5, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Guangyu Huang, Haitao Liu, Chandra Mouli, Justin B. Dorhout, Sanh D. Tang, Akira Goda
  • Patent number: 10490483
    Abstract: Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.
    Type: Grant
    Filed: March 7, 2016
    Date of Patent: November 26, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Deepak C. Pandey, Haitao Liu, Chandra Mouli
  • Publication number: 20190314922
    Abstract: A method of manufacturing Radio Frequency (RF) coil for multi-driven RF based-ve Ion source includes the steps of: (a) manufacturing a tube using stainless steel grade as a substrate material; (b) coating the tube; and (c) joining a plurality of coils produced by step (a) and step (b) by orbital TIG welding process.
    Type: Application
    Filed: August 8, 2018
    Publication date: October 17, 2019
    Inventors: Jaydeep Joshi, Chandra Mouli Rotti, Arun Kumar Chakraborty, Mainak Bandyopadhyay, Agrajit Gahlaut, Milind Kumar Patel, Venkata Nagaraju Muvvala, Deepak Kumar Parmar
  • Publication number: 20190312047
    Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.
    Type: Application
    Filed: May 23, 2019
    Publication date: October 10, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Haitao Liu, Chandra Mouli, Sergei Koveshnikov, Dimitrios Pavlopoulos, Guangyu Huang
  • Patent number: 10418379
    Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.
    Type: Grant
    Filed: April 4, 2018
    Date of Patent: September 17, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Guangyu Huang, Haitao Liu, Chandra Mouli, Justin B. Dorhout, Sanh D. Tang, Akira Goda
  • Publication number: 20190280046
    Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
    Type: Application
    Filed: May 28, 2019
    Publication date: September 12, 2019
    Inventor: Chandra Mouli
  • Publication number: 20190259769
    Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.
    Type: Application
    Filed: April 30, 2019
    Publication date: August 22, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Srinivas Pulugurtha, Rajesh N. Gupta
  • Patent number: 10388864
    Abstract: Some embodiments include a transistor having a drain region and a source region. A conductive gate is between the source and drain regions. First channel material is between the gate and the source region. The first channel material is spaced from the gate by one or more insulative materials. Second channel material is between the first channel material and the source region, and directly contacts the source region. The first and second channel materials are transition metal chalcogenide. One of the source and drain regions is a hole reservoir region and the other is an electron reservoir region. Tunnel dielectric material may be between the first and second channel materials.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: August 20, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Gurtej S. Sandhu, Chandra Mouli
  • Publication number: 20190253529
    Abstract: A method and system for a content broker, including a unified object index, where the content broker is coupled to the unified object index and receives, from a requesting entity, a request to perform an action on an object and the object is stored in the content repository. The method further including obtaining the object associated with the request from a content repository, determining, using the unified object index, a normalized object type associated with the object, obtaining a governance rule based on the normalized object type, and servicing the request using the governance rule.
    Type: Application
    Filed: April 29, 2019
    Publication date: August 15, 2019
    Inventors: Michael T. Mohen, Raman Walia, Chandra Mouli Addaguduru, Pardeep Kumar
  • Patent number: 10381365
    Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.
    Type: Grant
    Filed: August 15, 2017
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Haitao Liu, Chandra Mouli, Sergei Koveshnikov, Dimitrios Pavlopoulos, Guangyu Huang
  • Patent number: 10381357
    Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.
    Type: Grant
    Filed: July 24, 2018
    Date of Patent: August 13, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Srinivas Pulugurtha, Rajesh N. Gupta
  • Patent number: 10362146
    Abstract: A method and system for a content broker, including a unified object index, where the content broker is coupled to the unified object index and receives, from a requesting entity, a request to perform an action on an object and the object is stored in the content repository. The method further including obtaining the object associated with the request from a content repository, determining, using the unified object index, a normalized object type associated with the object, obtaining a governance rule based on the normalized object type, and servicing the request using the governance rule.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: July 23, 2019
    Assignee: Open Text Corporation
    Inventors: Michael T. Mohen, Raman Walia, Chandra Mouli Addaguduru, Pardeep Kumar
  • Patent number: 10297612
    Abstract: A vertical ferroelectric field effect transistor construction comprises an isolating core. A transition metal dichalcogenide material encircles the isolating core and has a lateral wall thickness of 1 monolayer to 7 monolayers. A ferroelectric gate dielectric material encircles the transition metal dichalcogenide material. Conductive gate material encircles the ferroelectric gate dielectric material. The transition metal dichalcogenide material extends elevationally inward and elevationally outward of the conductive gate material. A conductive contact is directly against a lateral outer sidewall of the transition metal dichalcogenide material that is a) elevationally inward of the conductive gate material, or b) elevationally outward of the conductive gate material. Additional embodiments are disclosed.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: May 21, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Gurtej S. Sandhu
  • Patent number: 10269805
    Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.
    Type: Grant
    Filed: February 13, 2018
    Date of Patent: April 23, 2019
    Assignee: Micron Technology, Inc.
    Inventors: Deepak Chandra Pandey, Haitao Liu, Chandra Mouli, Sanh D. Tang
  • Publication number: 20190067298
    Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.
    Type: Application
    Filed: July 24, 2018
    Publication date: February 28, 2019
    Applicant: Micron Technology, Inc.
    Inventors: Kamal M. Karda, Chandra Mouli, Srinivas Pulugurtha, Rajesh N. Gupta