Abstract: A data storage system having non-volatile media, a buffer memory, a processing device, and a data pre-fetcher. The data pre-fetcher receives commands to be executed in the data storage system, provides the commands as input to a predictive model, obtains at least one command identified for pre-fetching, as output from the predictive model having the commands as input. Prior to the command being executed in the data storage device, the data pre-fetcher retrieves, from the non-volatile memory, at least a portion of data to be used in execution of the command; and stores the portion of data in the buffer memory. The retrieving and storing the portion of the data can be performed concurrently with the execution of many commands before the execution of the command, to reduce the latency impact of the command on other commands that are executed concurrently with the execution of the command.

Abstract: A method and system for a content broker, including a unified object index, where the content broker is coupled to the unified object index and receives, from a requesting entity, a request to perform an action on an object and the object is stored in the content repository. The method further including obtaining the object associated with the request from a content repository, determining, using the unified object index, a normalized object type associated with the object, obtaining a governance rule based on the normalized object type, and servicing the request using the governance rule.

Abstract: A computing system includes a server. The server is communicatively coupled to a data repository and is configured to store a data in the data repository. The server is further configured to receive a first authentication information, the first authentication information comprising a login and a password for an entity, and to receive a second authentication information, the second authentication information comprising at least one identifying information generated by a hardware authentication device. The server is further configured to execute a hardware-based authentication as a service process, the authentication as a service process configured to use the first and the second authentication information as input to authenticate the entity, and to provide computing resources to the entity if the entity is successfully authenticated.

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

Abstract: Hardware controls associated with features of a scanner are removed, and a combined scanner and transaction terminal is provided without the hardware controls. Operations associated with the removed hardware controls are graphically depicted as selectable window options within scanner-generated windows. The scanner generated windows are provided as a projected human interface for the missing hardware controls. The projected human interface is provided with and accessible from a display that includes transaction windows produced by transaction software of the transaction terminal, such that the selectable window options are always accessible from the display during transaction processing performed by the transaction software.

Abstract: A method and system for managing document dissemination are disclosed, including obtaining a plurality of operation logs from a plurality of local agents, where each of the plurality of local agents is executing on one of a plurality of clients. The method further includes identifying a document stored on a client of the plurality of clients, determining, using at least one of the plurality of operation logs, a dissemination path of the document between the plurality of clients, and performing an action based on the dissemination path of the document.

Abstract: A control system for a machine operating on a worksite includes a telemetry module associated with the machine. The telemetry module generates signals indicative of operational data of the machine. A controller communicably coupled to the telemetry module receives the signals indicative of the operational data from the telemetry module. The controller processes the received signals to create a data model. The controller identifies multiple operational zones over the worksite based at least on an analysis of the created data model. The controller determines occurrence of work cycles of the machine over the worksite based at least on the identified operational zones. The controller determines productivity data of the worksite based at least on the identified work cycles. The controller controls the machine based on the determined productivity data.

Abstract: Some embodiments include an apparatus which has a wordline coupled with a transistor gate, and which has a compensator line extending along the wordline and spaced from the wordline by a dielectric region. A driver is coupled with the wordline, and a controller is coupled with the compensator line. The wordline is coupled with access transistors, and is operated at a first voltage while the access transistors are in an OFF state. The compensator line is operated at a second voltage while the wordline is at the first voltage; with the second voltage being greater than the first voltage. The wordline is operated at a third voltage while the access transistors are in an ON state, and the compensator line is operated at a fourth voltage while the wordline is at the third voltage. The third voltage may or may not be greater than the fourth voltage.

Abstract: Some embodiments include an apparatus having a transistor associated with a vertically-extending semiconductor pillar. The transistor includes an upper source/drain region within the vertically-extending semiconductor pillar, a lower source/drain region within the vertically-extending semiconductor pillar, and a channel region within the vertically-extending semiconductor pillar and between the upper and lower source/drain regions. The transistor also includes a gate along the channel region. A wordline is coupled with the gate of the transistor. A digit line is coupled with the lower source/drain region of the transistor. A programmable device is coupled with the upper source/drain region of the transistor. A body connection line is over the wordline and extends parallel to the wordline. The body connection line has a lateral edge that penetrates into the vertically-extending semiconductor material pillar. The body connection line is of a different composition than the semiconductor material pillar.

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

Abstract: Systems, methods, and apparatuses for performing analytics for equine-related conditions from fetlock sensors include receiving sensor data from one or more sensors attached to one or more fetlock wearable devices. Each of the one or more fetlock wearable devices are configured to attach to a fetlock of a respective limb of a horse. The analytics system compares the sensor data to one or more baseline measurement values. The analytics system detects a condition responsive to comparing the sensor data to one or more baseline measurement values. The analytics system transmits an alert to one or more remote devices responsive to detecting the condition.

Abstract: Apparatuses and methods ate disclosed herein for the formation of to capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate. Wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

Abstract: A device may include one or more processors to receive priority information corresponding to a virtual machine of a computing environment, receive a packet associated with the virtual machine, determine a priority associated with the virtual machine based on the priority information, the priority information indicating the priority associated with the virtual machine relative to other virtual machines of the computing environment, and/or assign the packet to a queue associated with a service node of the computing environment based on the virtual machine, the packet to be output from the queue based on the priority associated with the virtual machine.

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.

Abstract: Apparatuses and methods are disclosed herein for the formation of low capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate, wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

Abstract: A method of manufacturing Radio Frequency (RF) coil for multi-driven RF based-ve Ion source includes the steps of: (a) manufacturing a tube using stainless steel grade as a substrate material; (b) coating the tube; and (c) joining a plurality of coils produced by step (a) and step (b) by orbital TIG welding process.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: Some embodiments include an integrated structure having vertically-stacked conductive levels. Upper conductive levels are memory cell levels, and a lower conductive level is a select device level. Conductively-doped semiconductor material is under the select device level. Channel material extends along the memory cell levels and the select device level, and extends into the conductively-doped semiconductor material. A region of the channel material that extends into the conductively-doped semiconductor material is a lower region of the channel material and has a vertical sidewall. Tunneling material, charge-storage material and charge-blocking material extend along the channel material and are between the channel material and the conductive levels. The tunneling material, charge-storage material and charge-blocking material are not along at least a portion of the vertical sidewall of the lower region of the channel material, and the conductively-doped semiconductor material is directly against such portion.

Abstract: Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.