Abstract: In various implementations, a device surveys a scene and presents, within the scene, a extended reality (XR) environment including one or more assets that evolve over time (e.g., change location or age). Modeling such an XR environment at various timescales can be computationally intensive, particularly when modeling the XR environment over larger timescales. Accordingly, in various implementations, different models are used to determine the environment state of the XR environment when presenting the XR environment at different timescales.

Abstract: A memory device includes a plurality of groups of memory blocks, each group including a plurality of blocks, and each block including a plurality of memory units. A memory controller for the memory device performs operations including maintaining a count of valid memory units in the group for each group and maintaining a count of valid memory units in each block of the memory device. The operations further include selecting a first group based on a count of valid memory units and the first group including a target plurality of blocks. The operations further include selecting a first target block from the target plurality of blocks, determining whether the first target block is to be erased, and erasing the first target block in response to determining that the first target block is to be erased.

Abstract: Apparatuses and methods are disclosed herein for the formation of to capacitance through substrate via structures. An example apparatus includes an opening formed in a substrate. Wherein the opening has at least one sidewall, a first dielectric at least formed on the sidewall of the opening, a first conductor at least formed on the first dielectric, a second dielectric at least formed on the first conductor, and a second conductor at least formed on a sidewall of the second dielectric.

Abstract: Some embodiments include an integrated structure having a stack of alternating dielectric levels and conductive levels, and having vertically-stacked memory cells within the conductive levels. An opening extends through the stack. Channel material is within the opening and along the memory cells. At least some of the channel material contains germanium.

Abstract: Some embodiments include a memory cell with two transistors and one capacitor. The transistors are a first transistor and a second transistor. The capacitor has a first node coupled with a source/drain region of the first transistor, and has a second node coupled with a source/drain region of the second transistor. The memory cell has a first body region adjacent the source/drain region of the first transistor, and has a second body region adjacent the source/drain region of the second transistor. A first body connection line couples the first body region of the memory cell to a first reference voltage. A second body connection line couples the second body region of the memory cell to a second reference voltage. The first and second reference voltages may be the same as one another, or may be different from one another.

Abstract: In some implementations, a method includes obtaining an objective for a computer-generated reality (CGR) representation of an objective-effectuator. In some implementations, the objective is associated with a plurality of time frames. In some implementations, the method includes determining a plurality of candidate plans that satisfy the objective. In some implementations, the method includes selecting a first candidate plan of the plurality of candidate plans based on a selection criterion. In some implementations, the method includes effectuating the first candidate plan in order to satisfy the objective. In some implementations, the first candidate plan triggers the CGR representation of the objective-effectuator to perform a series of actions over the plurality of time frames associated with the objective.

Abstract: Hardware controls associated with features of a scanner are removed, and a combined scanner and transaction terminal is provided without the hardware controls. Operations associated with the removed hardware controls are graphically depicted as selectable window options within scanner-generated windows. The scanner generated windows are provided as a projected human interface for the missing hardware controls. The projected human interface is provided with and accessible from a display that includes transaction windows produced by transaction software of the transaction terminal, such that the selectable window options are always accessible from the display during transaction processing performed by the transaction software.

Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source/drain region.

Abstract: A bidirectional power converter includes flyback converter units connected in parallel, each having a controller and adapted to accumulate power from a primary side during an ON time and to deliver the accumulated power to a secondary side during an OFF time, the primary and secondary sides being interchangeable as to the direction of power conversion, the controller operating at a boundary between discontinuous and continuous conduction modes and performing valley switching when switching from OFF to ON, one converter unit operating as a master wherein the controller is adapted to control the length of ON time in order to feedback-control an overall current output of the converter, and each other converter unit operating as a slave wherein the controller controls the length of ON time in order to feedback-control a phase delay of ON time of the slave relative to ON time of another converter unit.

Abstract: A computing system includes a server. The server is communicatively coupled to a data repository and is configured to store a data in the data repository. The server is further configured to receive a first authentication information, the first authentication information comprising a login and a password for an entity, and to receive a second authentication information, the second authentication information comprising at least one identifying information generated by a hardware authentication device. The server is further configured to execute a hardware-based authentication as a service process, the authentication as a service process configured to use the first and the second authentication information as input to authenticate the entity, and to provide computing resources to the entity if the entity is successfully authenticated.

Abstract: A computing system includes a server. The server is communicatively coupled to a data repository and is configured to store a data in the data repository. The server is further configured to receive a first authentication information, the first authentication information comprising a login and a password for an entity, and to receive a second authentication information, the second authentication information comprising at least one identifying information generated by a hardware authentication device. The server is further configured to execute a hardware-based authentication as a service process, the authentication as a service process configured to use the first and the second authentication information as input to authenticate the entity, and to provide computing resources to the entity if the entity is successfully authenticated.

Abstract: Field-effect transistors, and methods of forming such field-effect transistors, including a gate dielectric overlying a semiconductor material, and a control gate overlying the gate dielectric, wherein the control gate includes an instance of a first polycrystalline silicon-containing material consisting essentially of polycrystalline silicon, and an instance of a second polycrystalline silicon-containing material selected from a group consisting of polycrystalline silicon-germanium and polycrystalline silicon-germanium-carbon.

Abstract: In some implementations, a method includes obtaining environmental data corresponding to a physical environment. In some implementations, the method includes determining, based on the environmental data, a bounding surface of the physical environment. In some implementations, the method includes detecting a physical element located within the physical environment based on the environmental data. In some implementations, the method includes determining a semantic label for the physical element based on at least a portion of the environmental data corresponding to the physical element. In some implementations, the method includes generating a semantic construction of the physical environment based on the environmental data. In some implementations, the semantic construction of the physical environment includes a representation of the bounding surface, a representation of the physical element and the semantic label for the physical element.

Abstract: Some embodiments include an integrated assembly having a semiconductor material with a more-doped region adjacent to a less-doped region. A two-dimensional material is between the more-doped region and a portion of the less-doped region. Some embodiments include an integrated assembly which contains a semiconductor material, a metal-containing material over the semiconductor material, and a two-dimensional material between a portion of the semiconductor material and the metal-containing material. Some embodiments include a transistor having a first source/drain region, a second source/drain region, a channel region between the first and second source/drain regions, and a two-dimensional material between the channel region and the first source; drain region.

Abstract: In some implementations, a method includes obtaining, by a virtual intelligent agent (VIA), a perceptual property vector (PPV) for a graphical representation of a physical element. In some implementations, the PPV includes one or more perceptual characteristic values characterizing the graphical representation of the physical element. In some implementations, the method includes instantiating a graphical representation of the VIA in a graphical environment that includes the graphical representation of the physical element and an affordance that is associated with the graphical representation of the physical element. In some implementations, the method includes generating, by the VIA, an action for the graphical representation of the VIA based on the PPV. In some implementations, the method includes displaying a manipulation of the affordance by the graphical representation of the VIA in order to effectuate the action generated by the VIA.

Abstract: In some implementations, a method includes obtaining a semantic construction of a physical environment. In some implementations, the semantic construction of the physical environment includes a representation of a physical element and a semantic label for the physical element. In some implementations, the method includes obtaining a graphical representation of the physical element. In some implementations, the method includes synthesizing a perceptual property vector (PPV) for the graphical representation of the physical element based on the semantic label for the physical element. In some implementations, the PPV includes one or more perceptual characteristic values characterizing the graphical representation of the physical element. In some implementations, the method includes compositing an affordance in association with the graphical representation of the physical element.

Abstract: In one implementation, a method of generating environment states is performed by a device including one or more processors and non-transitory memory. The method includes displaying an environment including an asset associated with a neural network model and having a plurality of asset states. The method includes receiving a user input indicative of a training request. The method includes selecting, based on the user input, a training focus indicating one or more of the plurality of asset states. The method includes generating a set of training data including a plurality of training instances weighted according to the training focus. The method includes training the neural network model on the set of training data.

Abstract: A field effect transistor construction includes a semiconductive channel core. A source/drain region is at opposite ends of the channel core. A gate is proximate a periphery of the channel core. A gate insulator is between the gate and the channel core. The gate insulator has local regions radially there-through that have different capacitance at different circumferential locations relative to the channel core periphery. Additional constructions, and methods, are disclosed.

Abstract: Some embodiments include methods of forming diodes in which a first electrode is formed to have a pedestal extending upwardly from a base. At least one layer is deposited along an undulating topography that extends across the pedestal and base, and a second electrode is formed over the least one layer. The first electrode, at least one layer, and second electrode together form a structure that conducts current between the first and second electrodes when voltage of one polarity is applied to the structure, and that inhibits current flow between the first and second electrodes when voltage having a polarity opposite to said one polarity is applied to the structure. Some embodiments include diodes having a first electrode that contains two or more projections extending upwardly from a base, having at least one layer over the first electrode, and having a second electrode over the at least one layer.