Patents by Inventor Chandrasekharan Kothandaraman

Chandrasekharan Kothandaraman has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • CMOS TRANSISTOR BIAS TEMPERATURE INSTABILITY BASED CHIP IDENTIFIER
    Publication number: 20160172011
    Abstract: Methods and devices for providing unclonable chip identification are provided. An integrated circuit device includes: a first transistor having a first gate oxide thickness; a second transistor having a second gate oxide thickness different than the first gate oxide thickness; and a reading circuit connected to the first transistor and the second transistor, wherein the reading circuit reads a difference in threshold voltage between the first transistor and the second transistor.
    Type: Application
    Filed: December 12, 2014
    Publication date: June 16, 2016
    Inventors: Dimitris P. IOANNOU, Chandrasekharan KOTHANDARAMAN
  • Undiscoverable physical chip identification
    Patent number: 9298950
    Abstract: Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.
    Type: Grant
    Filed: October 30, 2014
    Date of Patent: March 29, 2016
    Assignee: International Business Machines Corporation
    Inventors: Daniel Jacob Fainstein, Chandrasekharan Kothandaraman
  • Non-volatile memory based on retention modulation
    Patent number: 9208878
    Abstract: A mechanism that provides a source of reliability concern is leveraged to establish a non-volatile memory element. A memory cell may be programmed to have a longer retention time or a shorter retention time. Such mechanisms include, but are not limited to, threshold voltage modulation by charge trapping in the gate dielectric of an access transistor of a dynamic random access memory (DRAM) cell. A memory cell is programmed with a voltage pulse into a long retention time mode or into a short retention time mode. The programmed mode of each memory cell may be read by storing electrical charges in the DRAM cells, and by measuring whether the electrical charges remain after a threshold retention time. Further, a dual mode memory cell may be operated as a conventional DRAM cell, or as a non-volatile memory storing retention time as data.
    Type: Grant
    Filed: March 25, 2014
    Date of Patent: December 8, 2015
    Assignee: International Business Machines Corporation
    Inventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman
  • Three-terminal antifuse structure having integrated heating elements for a programmable circuit
    Patent number: 9184129
    Abstract: The present invention provides antifuse structures having an integrated heating element and methods of programming the same, the antifuse structures comprising first and second conductors and a dielectric layer formed between the conductors, where one or both of the conductors functions as both a conventional antifuse conductor and as a heating element for directly heating the antifuse dielectric layer during programming.
    Type: Grant
    Filed: January 11, 2011
    Date of Patent: November 10, 2015
    Assignee: GLOBALFOUNDRIES U.S. 2 LLC
    Inventors: Byeongju Park, Subramanian S. Iyer, Chandrasekharan Kothandaraman
  • Through-substrate via shielding
    Patent number: 9177923
    Abstract: A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer.
    Type: Grant
    Filed: October 21, 2014
    Date of Patent: November 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daeik Kim, Chandrasekharan Kothandaraman, Chung-Hsun Lin, John M. Safran
  • NON-VOLATILE MEMORY BASED ON RETENTION MODULATION
    Publication number: 20150279462
    Abstract: A mechanism that provides a source of reliability concern is leveraged to establish a non-volatile memory element. A memory cell may be programmed to have a longer retention time or a shorter retention time. Such mechanisms include, but are not limited to, threshold voltage modulation by charge trapping in the gate dielectric of an access transistor of a dynamic random access memory (DRAM) cell. A memory cell is programmed with a voltage pulse into a long retention time mode or into a short retention time mode. The programmed mode of each memory cell may be read by storing electrical charges in the DRAM cells, and by measuring whether the electrical charges remain after a threshold retention time. Further, a dual mode memory cell may be operated as a conventional DRAM cell, or as a non-volatile memory storing retention time as data.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 1, 2015
    Applicant: International Business Machines Corporation
    Inventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman
  • PHYSICALLY UNCLONABLE FUSE USING A NOR TYPE MEMORY ARRAY
    Publication number: 20150278551
    Abstract: A method for identifying an unclonable chip uses hardware intrinsic keys and authentication responses employing intrinsic parameters of memory cells invariant and unique to the unclonable chip, wherein intrinsic parameters that characterize the chip can extend over its lifetime. The memory cells having a charge-trap behavior are arranged in an NOR type memory array, allowing to create a physically unclonable fuse (PUF) generation using non-programmed memory cells, while stringing non-volatile bits in programmed memory cells. The non-volatile memory cell bits are used for error-correction-code (ECC) for the generated PUF. The invention can further include a public identification using non-volatile bits, allowing hand shaking authentication using computer with dynamic challenge.
    Type: Application
    Filed: March 25, 2014
    Publication date: October 1, 2015
    Applicant: International Business Machines Corporation
    Inventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman, Derek H. Leu, Sami Rosenblatt
  • STRUCTURE AND METHOD TO DETERMINE THROUGH SILICON VIA BUILD INTEGRITY
    Publication number: 20150204932
    Abstract: A structure to detect changes in the integrity of vertical electrical connection structures including a semiconductor layer and an electrically conductive material extending through an entire depth of the semiconductor layer. The electrically conductive material has a geometry that encloses a pedestal portion of the semiconductor layer within an interior perimeter of the electrically conductive material. At least one semiconductor device is present on the pedestal portion of the semiconductor layer within the perimeter of the electrically conductive material.
    Type: Application
    Filed: January 22, 2014
    Publication date: July 23, 2015
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Troy L. Graves-Abe, Chandrasekharan Kothandaraman, Conal E. Murray
  • Through-substrate via shielding
    Patent number: 9070698
    Abstract: A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer.
    Type: Grant
    Filed: November 1, 2012
    Date of Patent: June 30, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daeik Kim, Chandrasekharan Kothandaraman, Chung-Hsun Lin, John M. Safran
  • EMBEDDED CHARGE TRAP MULTI-TIME-PROGRAMMABLE-READ-ONLY-MEMORY FOR HIGH PERFORMANCE LOGIC TECHNOLOGY
    Publication number: 20150138891
    Abstract: An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT0) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a bitline (BL) running in a second direction; creating two dimensional meshed source line network running in the first and second directions, in a standby state, wherein BLs and MSLN are at a voltage (VDD), and the WLs are at ground; storing a data bit by trapping charges in a dielectric of a target MOSFET, VT0 of target MOSFET increasing to another voltage (VT1) by a predetermined amount (?VT); reading a data bit by using the MOSFET threshold voltage having one of VT0 or VT1 to determine a trapped or de-trapped charge state, and resetting the data bit to a de-trapped state by de-trapping the charge.
    Type: Application
    Filed: November 20, 2013
    Publication date: May 21, 2015
    Applicant: International Business Machiness Corporation
    Inventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman, Derek H. Leu, Dan Moy
  • Embedded charge trap multi-time-programmable-read-only-memory for high performance logic technology
    Patent number: 9025386
    Abstract: An embedded Multi-Time-Read-Only-Memory having a (MOSFET) cells' array having an initial threshold voltage (VT0) including the MOSFETs arranged in a row and column matrix, having gates in each row coupled to a wordline (WL) running in a first direction and sources in each one of the columns coupled to a bitline (BL) running in a second direction; creating two dimensional meshed source line network running in the first and second directions, in a standby state, wherein BLs and MSLN are at a voltage (VDD), and the WLs are at ground; storing a data bit by trapping charges in a dielectric of a target MOSFET, VT0 of target MOSFET increasing to another voltage (VT1) by a predetermined amount (?VT); reading a data bit by using the MOSFET threshold voltage having one of VT0 or VT1 to determine a trapped or de-trapped charge state, and resetting the data bit to a de-trapped state by de-trapping the charge.
    Type: Grant
    Filed: November 20, 2013
    Date of Patent: May 5, 2015
    Assignee: International Business Machines Corporation
    Inventors: Subramanian S. Iyer, Toshiaki Kirihata, Chandrasekharan Kothandaraman, Derek H. Leu, Dan Moy
  • Structures and Methds for Monitoring Dielectric Reliability With Through-Silicon Vias
    Publication number: 20150115982
    Abstract: Embodiments of the present invention provide a variety of structures and method for detecting abnormalities in the back-end-of-line (BEOL) stack and BEOL structures located in close proximity to through-silicon vias (TSVs) in a 3D integrated chip. The detected abnormalities may include stress, strain, and damage that will affect metallization continuity, interfacial integrity within a metal level, proximity accuracy of the TSV placement, and interlevel dielectric integrity and metallization-to-TSV dielectric integrity. Additionally, these structures in conjunction with each other are capable of determining the range of influence of the TSV. That is, how close to the TSV that a BEOL line (or via) needs to be in order to be influenced by the TSV.
    Type: Application
    Filed: October 31, 2013
    Publication date: April 30, 2015
    Applicant: International Business Machines Corporation
    Inventors: Fen Chen, Mukta G. Farooq, John A. Griesemer, Chandrasekharan Kothandaraman, John Matthew Safran, Timothy Dooling Sullivan
  • Through-silicon-via with sacrificial dielectric line
    Patent number: 8975910
    Abstract: A TSV structure, method of making the TSV structure and methods of testing the TSV structure. The structure including: a trench extending from a top surface of a semiconductor substrate to a bottom surface of the semiconductor substrate, the trench surrounding a core region of the semiconductor substrate; a dielectric liner on all sidewalls of the trench; and an electrical conductor filling all remaining space in the trench, the dielectric liner electrically isolating the electrical conductor from the semiconductor substrate and from the core region.
    Type: Grant
    Filed: April 27, 2012
    Date of Patent: March 10, 2015
    Assignee: International Business Machines Corporation
    Inventors: Troy L. Graves-Abe, Benjamin A. Himmel, Chandrasekharan Kothandaraman, Norman W. Robson
  • UNDISCOVERABLE PHYSICAL CHIP IDENTIFICATION
    Publication number: 20150059008
    Abstract: Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.
    Type: Application
    Filed: October 30, 2014
    Publication date: February 26, 2015
    Applicant: International Business Machines Corporation
    Inventors: Daniel Jacob Fainstein, Chandrasekharan Kothandaraman
  • THROUGH-SUBSTRATE VIA SHIELDING
    Publication number: 20150035589
    Abstract: A semiconductor apparatus includes a substrate structure including a silicon substrate layer, a conductive through-substrate via extending through the silicon substrate layer. The apparatus further includes a semiconductor device located in the substrate structure and a conductive wall located between the through-substrate via and the semiconductor device. The conductive wall is in electrical contact with the silicon substrate layer.
    Type: Application
    Filed: October 21, 2014
    Publication date: February 5, 2015
    Inventors: Daeik Kim, Chandrasekharan Kothandaraman, Chung-Hsun Lin, John M. Safran
  • Undiscoverable physical chip identification
    Patent number: 8950008
    Abstract: Methods and circuits for undiscoverable physical chip identification are disclosed. Embodiments of the present invention provide an intrinsic bit element that comprises two transistors. The two transistors form a pair in which one transistor has a wide variability in threshold voltage and the other transistor has a narrow variability in threshold voltage. The wide variability is achieved by making a transistor with a smaller width and length than the other transistor in the pair. The variation of the threshold voltage of the wide variability transistor means that in the case of copies of intrinsic bit elements being made, some of the “copied” wide variability transistors will have significantly different threshold voltages, causing some of the intrinsic bit elements of a copied chip to read differently than in the original chip from which they were copied.
    Type: Grant
    Filed: July 30, 2012
    Date of Patent: February 3, 2015
    Assignee: International Business Machines Corporation
    Inventors: Daniel Jacob Fainstein, Chandrasekharan Kothandaraman
  • Anticipatory implant for TSV
    Patent number: 8927427
    Abstract: A method including introducing a dopant into a region of a substrate, etching a deep trench in the substrate through the region, gettering impurities introduced during etching of the deep trench using a pentavalent ion formed from a reaction between an element of the substrate and the dopant, wherein the charge of the pentavalent ion attracts the impurities, and filling the deep trench with a conductive material.
    Type: Grant
    Filed: April 29, 2013
    Date of Patent: January 6, 2015
    Assignee: International Business Machines Corporation
    Inventors: Troy L. Graves-Abe, Brian J. Greene, Chandrasekharan Kothandaraman
  • TSV structure with a built-in U-shaped FET transistor for improved characterization
    Patent number: 8907410
    Abstract: A through-the silicon via (TSV) structure providing a built-in TSV U-shaped FET that includes an annular gate shaped as a TSV partially embedded in a substrate, the annular gate having an inner and an outer surface bound by an oxide layer; a drain formed on an isolated epitaxial layer on top of the substrate conformally connecting the gate oxide layer surrounding the inner annular surface of the TSV; a source partially contacting said gate oxide layer conformally contacting gate oxide layer surrounding the outer surface of the TSV.
    Type: Grant
    Filed: April 25, 2013
    Date of Patent: December 9, 2014
    Assignee: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Sami Rosenblatt, Geng Wang
  • ANTICIPATORY IMPLANT FOR TSV
    Publication number: 20140319694
    Abstract: A method including implanting a region of a substrate with a dopant, and forming a through-substrate via in the substrate adjacent to a device, the through-substrate via passing through the region.
    Type: Application
    Filed: April 29, 2013
    Publication date: October 30, 2014
    Applicant: International Business Machines Corporation
    Inventors: Troy L. Graves-Abe, Brian J. Greene, Chandrasekharan Kothandaraman
  • TSV Structure With A Built-In U-Shaped FET Transistor For Improved Characterization
    Publication number: 20140319600
    Abstract: A through-the silicon via (TSV) structure providing a built-in TSV U-shaped FET that includes an annular gate shaped as a TSV partially embedded in a substrate, the annular gate having an inner and an outer surface bound by an oxide layer; a drain formed on an isolated epitaxial layer on top of the substrate conformally connecting the gate oxide layer surrounding the inner annular surface of the TSV; a source partially contacting said gate oxide layer conformally contacting gate oxide layer surrounding the outer surface of the TSV.
    Type: Application
    Filed: April 25, 2013
    Publication date: October 30, 2014
    Applicant: International Business Machines Corporation
    Inventors: Chandrasekharan Kothandaraman, Sami Rosenblatt, Geng Wang