PROGRAMMABLE ELECTRONIC FUSE
A programmable device (eFuse), includes: a substrate (10); an insulator (13) on the substrate; an elongated semiconductor material (12) on the insulator, the elongated semiconductor material having a first end (12a), a second end (12b), a fuse link (11) between the ends, and an upper surface S. The semiconductor material includes a dopant having a concentration of at least 10*17/cc. The first end (12a) is wider than the second end (12b), and a metallic material is disposed on the upper surface. The metallic material is physically migratable along the upper surface responsive to an electrical current I flowable through the semiconductor material and through the metallic material.
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This application is a continuation of U.S. patent application Ser. No. 10/904,058, filed Oct. 21, 2004.
TECHNICAL FIELDThe present invention relates to programmable semiconductor devices and, more particularly, to such devices usable as semiconductor electronic fuses (eFuses).
BACKGROUND ARTSemiconductor eFuses in general are known. The word fuse or eFuse will be used interchangeably in this specification. Specifically, eFuse in this application refers to fuses that increase the resistance of a circuit path when subjected to a programming current.
However, known eFuses have not proven to be entirely satisfactory. Programming in, for example, silicon-based semiconductor devices (e.g., fuses) can result in post collateral damage of neighboring structures. This result typically forces a fuse pitch, or fuse cavity, set of rules that do not scale well with the technology feature rules from one generation to the next. Thus, fuse density and effectiveness of fuse repair, replacement, or customization are limited. Typically, such damage is caused by particulates from fuse blow. Another class of fuses having a high resistance from an unprogrammed state change to a programmed state having a low resistance, is known as “antifuse”. See, for example, U.S. Pat. No. 5,334,880, Low Voltage Programmable Storage Element, by Abadeer, et al., which is incorporated here in its entirety.
Semiconductor chips typically have many fuses depending on the particular device; the number of fuses can range from tens to thousands. Such fuses contain an initial resistance the number of fuses can range from tens to thousands. Such fuses contain an initial resistance distribution of R0±ΔR0, and a programmed resistance distribution of Rp±ΔRp. The ±ΔRp causes fuse read instability because this parameter is statistical in nature. The variations that cause the R0 and Rp. distributions to approach each other cause practical limitations in interrogating a programmed fuse through a standard CMOS latching circuit. To overcome these limitations, the prior art has included (for example) additional fuses as reference elements in order to discriminate between a programmed and an unprogrammed fuse. Such practices result in unwanted growth in the fuse bank area.
SUMMARY OF THE INVENTIONThe present invention overcomes this and other drawbacks by employing a device or fuse structure of composite layers of materials that migrate by a specific type of physical diffusion process under an applied current. This differs from the melting or vaporizing type common with many known fuses during a programming event. The material (e.g., CoSi2 or NiSi2) that visually migrates (mostly by electromigration) causes the change in the resistance of the fuse, while not causing collateral damage during its migration or material reformation, and has a programmed state where ±ΔRp is preferably small and close to zero (i.e the programmed fuse resistances are tightly distributed). Thus, the present invention allows for individual fuses to discriminate among themselves on the basis of programming and to eliminate unwanted reference fuse elements, as well as the circuitry used to bias and compare against the reference fuse elements. A “reliable” eFuse technology in this application means a fuse structure and/or programming methodology that result in a large population of eFuses to achieve a programmed resistance objective (greater than some resistance value or a nominal value and a sigma etc.) without melting or other process that can cause collateral damage.
U.S. Pat. Nos. 6,008,523, 6,432,760, 6,433,404 and 6,624,499 discuss aspects of an eFuse, relevant to the present invention. The patents are assigned to the assignee of the present application, and are fully incorporated herein. U.S. Pat. No. 6,642,601 teaches a specific eFuse improvement, and in particular teaches the use of thinner layers in the fuse link regions as compared to the rest of the fuse. The disadvantage of this eFuse ('601) is that in order to create such a structure, additional process steps including mask levels and lithographic processes are required.
A method of programming an eFuse according to the present invention includes flowing an electrical current I through the fuse having a metallic material such as a semiconductor alloy (40) disposed on a doped semiconductor line (12), for a time period such that a portion of the semiconductor alloy migrates from a first end (12a) of the device to a location proximate to a second end (12b) of the device. Further, the inventors believe that the dopants in portions of the doped semiconductor line 12 are removed during the programming cycle enabling a high final resistance.
The applicants of the present invention discovered that several parameters determine if the fuse will be a reliable eFuse. Such parameters include, for example, fuse geometry, resistance of the layers, thickness of the layers, electrode shapes, programming current and type of insulator coatings. The applicants believe that the effect or influence of these parameters on device operation can be unexpected. See, for example, “Electrically Programmable Fuse (eFuse) Using Electromigration in Silicides” by Kothandaraman, et al., IEEE Electron Device Letters, Vol 23, No. 9, September 2002, which is incorporated in it entirety herein.
Accordingly, it is an object of the present invention to provide a method of fabricating a reliable programmable eFuse, which method is readily compatible with various standard MOS manufacturing processes, including those used for DRAM and Logic devices.
An additional object of the present invention is to provide a method of programming an eFuse which reduces collateral damages to neighboring structures.
Another object of the present invention is to provide a reliable eFuse design that can be programmed using low voltages of 5 volts and less.
Still another object of the present invention is to establish structural parameters for a reliable eFuse.
Further and still other objects of the present invention will become more readily apparent when the following detailed description is taken in conjunction with the accompanying drawings.
Using the finite element model of
The inventors have studied fuses with ranges of thicknesses for polysilicon and silicide that can be used to build a reliable eFuse, listed in Table 2 (
Using
resistance of the metallic material (40) are much less than the resistivity and resistance of the semiconductor line (12). Preferably, the resistivity of the material (40) is in a range of approximately (±10%) 6 ohms per square to 12 ohms per square, while the resistivity of the line (12) is in a range of approximately 250 ohms per square to 350 ohms per square (P+ polysilicon).
Preferably, the resistivity of the material (40) and the line (12) in combination has an effective resistivity of 7 ohms per square to 13 ohms per square for logic.
During programming, i.e., under suitable current, voltage and time conditions, the material (40) migrates from the first end (12a) and the link (11), to a location proximate to the second end (12b) and accumulates; in addition, the heat generated in the semiconductor material makes it conducting and thus enables continued conduction of the current and continued movement of silicide in the direction of electron flow, even as the silicide becomes discontinuous. During this process, the dopants in the semiconductor are removed via electromigration in the direction of the current towards the second end (12b) as well as segregated into the STI region (13).
Using the methodology described earlier in conjunction with
invention. The program voltage is preferably 3.3 Volts, even though up to 5V can be used with the CMOS logic devices.
While there has been shown and described what is at present considered a preferred embodiment of the present invention, it will be readily understood by those skilled in the art that various changes and modification may be made therein without departing from the spirit and scope of the present invention which shall be limited only by the scope of the claims.
INDUSTRIAL APPLICABILITYThe present invention has applicability as E-fuses that may be employed during chip production, or within a deployed system to repair failing circuitry, or to customize a hardware or software application.
Claims
1. A programmable device, comprising:
- a substrate;
- an insulator on said substrate;
- an elongated semiconductor material on said insulator, said elongated semiconductor material having a first end, a second end, a fuse link between the ends, and an upper surface.
- wherein said semiconductor material includes a dopant having a concentration of at least 10*17/cc,
- said first end is wider than said second end, and
- a metallic material is disposed on said upper surface, said metallic material being physically migratable along said upper surface responsive to an electrical current I flowable through said semiconductor material and through said metallic material.
2. The programmable device of claim 1, wherein the dopant is “n” or “p” type and the semiconductor material is doped in the range of approximately 10*17/cc to approximately 10*21/cc.
3. A programmable device of claim 1, further comprising an insulating layer overlying the silicide layer, the insulating layer being non-reactive with the metallic layer during a programming of the device.
4. The programmable device as claimed in claim 1, further comprising an energy source connected to said elongated semiconductor material, for causing an electrical current to flow through said elongated semiconductor material and through said metallic material for a predetermined time, and for causing said metallic material to migrate along said upper surface.
5. The programmable device as claimed in claim 1, wherein said elongated semiconductor material is selected to have a thickness of about 120 nm
6. The programmable device as claimed in claim 1, where said semiconductor material is selected to have a substantially uniform thickness in the range of approximately 60 nm to approximately 250 nm
7. The programmable device as claimed in claim 1, wherein said fuse link has a length greater than five times the fuse link width.
8. The programmable device of claim 1, wherein said fuse link has a length that is less than 15 times the fuse link width.
9. The programmable device as claimed in claim 1, wherein said metallic material is a metallic silicide selected from the group consisting of Nickel silicide and Cobalt silicide.
10. The programmable device of claim 1, wherein the elongated semiconductor material is a polysilicon and the metallic material is a metallic alloy, and the ratio of resistivities of the polysilicon and metallic alloy ranges between 20 to 50, and preferably 30.
11. The programmable device of claim 1, wherein a thickness ratio of the semiconductor material and metallic material ranges between 3 to 8, and preferably about 6.
12. The programmable device of claim 1, wherein a non-reactive insulating layer of SiN is disposed above the metallic material.
13. The programmable device of claim 12, wherein the SiN has a thickness greater than 3000 angstroms.
14. The programmable device of claim 1, wherein the insulator has a substantially uniform thickness of approximately 3000 angstroms.
15. A programmable device for reliably achieving a post-programming resistance greater than 5 Kohms, said programmable device comprising:
- a substrate;
- an insulator on said substrate;
- an elongated semiconductor material having a constant first thickness and disposed on said insulator, said elongated semiconductor material having a first end, a second end, a fuse link between the ends, and an upper surface;
- a metallic material having a constant second thickness and disposed on said upper surface; and
- at least one programming transistor configured to supply an electrical current, I, having a magnitude between a first value and a second value through said elongated semiconductor material and through said metallic material;
- wherein said semiconductor material includes a dopant of one conductivity type at a concentration of at least 1017 dopants/cc, while not including any dopant of an opposite conductivity type; said first end is wider than said second end, and said metallic material being physically migratable along said upper surface responsive to said electrical current; wherein said first value is set between a first range of current level that causes a post-program resistance distribution that is wide and on a low side of approximately 5 Kohms and a second range of current level that causes said post-program resistance to be greater than 5 Kohms and tightly distributed without any rupture in said elongated semiconductor material; and wherein said second value is set between said second range of current level and a third range of current level that ruptures said elongated semiconductor material and said post-program resistance shows a two mode distribution.
Type: Application
Filed: Jan 16, 2009
Publication Date: Jul 16, 2009
Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION (Armonk, NY)
Inventors: Chandrasekharan Kothandaraman (Hopewell Junction, NY), Subramanian Iyer (Mount Kisco, NY)
Application Number: 12/355,056
International Classification: H01L 23/525 (20060101);