Abstract: A method of fabricating a device includes providing a plurality of fins extending from a substrate. In some embodiments, each fin of the plurality of fins includes a plurality of semiconductor channel layers. In various example, the method further includes performing an ion implantation process into a first fin of the plurality of fins to introduce a dopant species into a topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin. In some embodiments, the ion implantation process deactivates the topmost semiconductor channel layer of the plurality of semiconductor channel layers of the first fin.

Abstract: This disclosure provides systems, methods and apparatus, including computer programs encoded on computer storage media, for switching a secondary cell to a primary cell. A user equipment (UE) monitors a first radio condition of the UE for beams of a primary cell and a second radio condition for beams of one or more secondary cells configured for the UE in carrier aggregation. The UE transmits a request to configure a candidate beam of at least one candidate secondary cell as a new primary cell in response to the first radio condition not satisfying a first threshold and the second radio condition for the at least one candidate secondary cell satisfying a second threshold. A base station determines to reconfigure at least one secondary cell as the new primary cell. The base station and the UE perform a handover of the UE to the new primary cell.

Abstract: An identity certificate may be issued to a blockchain node. The issuance may include issuing a first identity certificate to a first terminal and receiving a second identity certificate issuance request that is from the first terminal. A second identity certificate may be issued to the first terminal, and a third identity certificate issuance request is received from the second terminal. A third identity certificate is issued to the second terminal, so that the second terminal forwards the third identity certificate to the third terminal.

Abstract: The disclosure provides a limit device and a robot using the same. The limit device comprises a first connecting member, a transmission rod and a second connecting member. The first connecting member comprising a first main body portion and two first connecting elements. The two first connecting elements are arranged at intervals. The two first connecting elements are respectively connected to the first main body. The transmission rod comprising a first end and a second end. The first end and the second end are arranged at intervals. The first end penetrates through one of the two first connecting elements. The second end penetrates through the other one of the two first connecting element. The second connecting member provided with two indexing buckles. The two indexing buckles are arranged at intervals, each of the indexing buckles comprises a first limiting groove and a second limiting groove.

Abstract: A light-folding element includes an object-side surface, an image-side surface, a reflection surface and a connection surface. The reflection surface is configured to reflect imaging light passing through the object-side surface to the image-side surface. The connection surface is connected to the object-side, image-side and reflection surfaces. The light-folding element has a recessed structure located at the connection surface. The recessed structure is recessed from the connection surface an includes a top end portion, a bottom end portion and a tapered portion located between the top end and bottom end portions. The top end portion is located at an edge of the connection surface. The tapered portion has two tapered edges located on the connection surface. The tapered edges are connected to the top end and bottom end portions. A width of the tapered portion decreases in a direction from the top end portion towards the bottom end portion.

Abstract: A device includes a semiconductive fin having source and drain regions and a channel region between the source and drain regions, a gate feature over the channel region of the semiconductive fin, a first spacer around the gate feature, source and drain features respectively in the source and drain regions of the semiconductive fin, an interlayer dielectric layer around the first spacer, and a void between the first spacer and the interlayer dielectric layer and spaced apart from the gate feature and the source and drain features.

Abstract: An interfacial structure, along with methods of forming such, are described. The structure includes a first interfacial layer having a first dielectric layer, a first conductive feature disposed in the first dielectric layer, and a first thermal conductive layer disposed on the first dielectric layer. The structure further includes a second interfacial layer disposed on the first interfacial layer. The second interfacial layer is a mirror image of the first interfacial layer with respect to an interface between the first interfacial layer and the second interfacial layer. The second interfacial layer includes a second thermal conductive layer disposed on the first thermal conductive layer, a second dielectric layer disposed on the second thermal conductive layer, and a second conductive feature disposed in the second dielectric layer.

Abstract: A semiconductor device and method for forming the semiconductor device are provided. In some embodiments, a semiconductor substrate comprises a device region. An isolation structure extends laterally in a closed path to demarcate the device region. A first source/drain region and a second source/drain region are in the device region and laterally spaced. A sidewall of the first source/drain region directly contacts the isolation structure at a first isolation structure sidewall, and remaining sidewalls of the first source/drain region are spaced from the isolation structure. A selectively-conductive channel is in the device region, and extends laterally from the first source/drain region to the second source/drain region. A plate comprises a central portion and a first peripheral portion. The central portion overlies the selectively-conductive channel, and the first peripheral portion protrudes from the central portion towards the first isolation structure sidewall.

Abstract: In example implementations, a computing device is provided. The computing device includes a system management bus, a controller communicatively coupled to the system management bus, a noise generating component communicatively coupled to the controller, a noise cancellation codec communicatively coupled to the system management bus, and a speaker communicatively coupled to the noise cancellation codec. The operating parameters of the noise generating component are provided to the controller. The noise cancellation codec is to receive the operating parameters of the noise generating component from the controller via the system management bus and to generate a noise cancellation signal based on the operating parameters. The speaker outputs the noise cancellation signal to cancel noise generated by the noise generating component.

Abstract: Embodiments of the present disclosure provide a method for forming semiconductor device structures. The method includes forming a fin structure having a stack of semiconductor layers comprising first semiconductor layers and second semiconductor layers alternatingly arranged, forming a sacrificial gate structure over a portion of the fin structure, removing the first and second semiconductor layers in a source/drain region of the fin structure that is not covered by the sacrificial gate structure, forming an epitaxial source/drain feature in the source/drain region, removing portions of the sacrificial gate structure to expose the first and second semiconductor layers, removing portions of the second semiconductor layers so that at least one second semiconductor layer has a width less than a width of each of the first semiconductor layers, forming a conformal gate dielectric layer on exposed first and second semiconductor layers, and forming a gate electrode layer on the conformal gate dielectric layer.

Abstract: An imaging lens assembly has an optical axis, and includes a plastic carrier element and an imaging lens element set. The plastic carrier element includes an object-side surface, an image-side surface, an outer surface and an inner surface. The object-side surface includes an object-side opening. The image-side surface includes an image-side opening. The inner surface is connected to the object-side opening and the image-side opening. The imaging lens element set is disposed in the plastic carrier element, and includes at least three lens elements, each of at least two adjacent lens elements of the lens elements includes a first axial assembling structure, the first axial assembling structures are corresponding to and connected to each other. A solid medium interval is maintained between the adjacent lens elements and the inner surface. The solid medium interval is directly contacted with the adjacent lens elements and the inner surface.

Abstract: A double side-scroll mouse device includes a housing unit, a main button unit, and a side scroll unit. The housing unit has a lower casing and a casing side skirt. The lower casing has spaced-apart first and second lateral face portions. The casing side skirt has a first operating wall extending upwardly from one of the first and second lateral face portions, and a second operating wall portion extending upwardly from the first operating wall portion. The side scroll unit includes a first scroll wheel member that is disposed on the first operating wall portion and that is rotatable about a first axis, and a second scroll wheel member that is disposed on the second operating wall portion and that is rotatable about a second axis being substantially perpendicular to the first axis.

Abstract: High voltage semiconductor devices are described herein. An exemplary semiconductor device includes a substrate, a first doped region disposed in the substrate and doped with a first doping polarity, and a second doped region disposed in the substrate and horizontally outside the first doped region. The second doped region is doped with a second doping polarity opposite to the first doping polarity. The semiconductor device further includes a third doped region disposed completely within the first doped region. The third doped region is doped with the second doping polarity. The semiconductor device further includes a first isolation structure disposed over the first doped region and spaced apart from the second doped region and the third doped region, a second isolation structure disposed over the first doped region and the third doped region, and a resistor disposed over the first isolation structure.

Abstract: A manufacturing method of a reflective display includes at least the following steps. A reflective display module having a display surface is provided. An adhesive is formed on the display surface of the reflective display module. A plurality of microstructures is formed on the adhesive. A cover plate is provided over the reflective display module, the microstructures, and the adhesive. The cover plate has a first surface, a second surface, and a third surface. The second surface is located between the first surface and the reflective display module, and the third surface is connected to the first surface and the second surface. The second surface of the cover plate is adhered to the adhesive having the microstructures thereon to bond the microstructures onto the second surface of the cover plate. A light source is disposed adjacent to the third surface of the cover plate.

Abstract: An antiaging assessment method for facial rejuvenation is provided. Firstly, a spatial relationship between various facial key points of an under-test facial image are precisely described. Consequently, a facial feature is obtained. The spatial relationship is an angle relationship or a length relationship. Then, a feature change comparison between the facial feature and reference feature is performed. Consequently, a feature change value is obtained. According to the at least one feature change value, a facial rejuvenation score index is acquired from a corresponding feature change value range of a facial rejuvenation score index data table. The present invention also provides an antiaging assessment device for facial rejuvenation.

Abstract: Disclosed herein are related to a device for performing neuromorphic computing. In one aspect, a device includes a back end of line layer including a three-dimensional memory array. The three-dimensional memory array may include a plurality of memory cells to store a plurality sets of weight values of a neural network model. In one aspect, the device includes a front end of line layer including a controller. The controller may apply one or more input voltages corresponding to an input to the neural network model to the three-dimensional memory array, and receive one or more output voltages from the three-dimensional memory array to perform computations of the neural network model.

Abstract: In some embodiments, a semiconductor device is provided. The semiconductor device includes an isolation structure disposed in a semiconductor substrate, where an inner perimeter of the isolation structure demarcates a device region of the semiconductor substrate. A gate is disposed over the device region, where an outer perimeter of the gate is disposed within the inner perimeter of the isolation structure. A first source/drain region is disposed in the device region and on a first side of the gate. A second source/drain region is disposed in the device region and on a second side of the gate opposite the first side. A silicide blocking structure partially covers the gate, partially covers the first source/drain region, and partially covers the isolation structure, where a first sidewall of the silicide blocking structure is disposed between first opposite sidewalls of the gate.

Abstract: A semiconductor device includes a substrate and a gate structure over the substrate. The semiconductor device includes a source in the substrate on a first side of the gate structure. The semiconductor device further includes a drain in the substrate on a second side of the gate structure. The semiconductor device further includes a first well having a first dopant type, wherein the first well contacts at least two surfaces of the source. The semiconductor device further includes a second well having the first dopant type, wherein the second well contacts at least two surfaces of the drain. The semiconductor device further includes a deep well below the first well and below the second well, wherein the second well extends between the first well and the deep well. In some embodiments, the deep well has a second dopant type, and the second dopant type is opposite the first dopant type.

Abstract: The present invention is related to an UV LED curing apparatus, and more particularly, to an UV LED curing apparatus with improved housing and switch controller. The light reflective inner casing is preferably provided as an effective UV light reflector and as a supporting substrate of the UV LED light source while being capable of transmitting heat from the UV LED light source away for further heat dissipation to the ambient by the outer casing. The outer casing is detachably attached to the inner casing and allows a greater user interaction for decorative and entertainment purposes while also being a protective and heat dissipation means.