Patents by Inventor Chang Hsieh

Chang Hsieh has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20170325001
    Abstract: A data processing method of a multimedia device is disclosed. The multimedia device pauses playback of multimedia data in response to a pause signal. The method includes: buffering the multimedia data before the pause signal is received to obtain prerecorded multimedia data; writing the prerecorded multimedia data into a storage unit in response to the pause signal; reading the prerecorded multimedia data from the storage unit in response to a playback signal; and playing the prerecorded multimedia data.
    Type: Application
    Filed: August 15, 2016
    Publication date: November 9, 2017
    Inventors: An-Chang Hsieh, Pei-Yu Chiang
  • Publication number: 20170322662
    Abstract: A display apparatus with touch sensing and force sensing functions includes a display panel, a first touch device, a conductive layer and a dielectric layer. The first touch device includes multiple touch sensing pads. The conductive layer includes multiple force sensing pads electrically connected to each other, where the touch sensing pads separately overlap the corresponding force sensing pads in a vertical projection direction. The dielectric layer is disposed between the conductive layer and the first touch device. The touch sensing pads, the dielectric layer and the force sensing pads form a force sensing device.
    Type: Application
    Filed: September 16, 2016
    Publication date: November 9, 2017
    Inventors: Yi-San HSIEH, Shih-Lun LAI, Wen-Chang HSIEH, I-Hsiung HUANG
  • Publication number: 20170316983
    Abstract: A method includes depositing an ESL on a substrate; patterning the ESL such that a first region of the substrate is covered thereby and a second region of the substrate is exposed within an opening of the etch stop layer; depositing a first dielectric layer on the ESL in the first region and on the substrate in the second region; patterning the first dielectric layer to form a first trench through the first dielectric layer in the first region; forming a metal feature in the first trench; depositing a second dielectric layer over the metal feature in the first region and over the first dielectric layer in the second region; and performing a patterning process to form a second trench through the second dielectric layer in the first region, and to form a third trench through the second and first dielectric layers in the second region.
    Type: Application
    Filed: February 16, 2017
    Publication date: November 2, 2017
    Inventors: Yuan-Yen Lo, Jhih-Yu Wang, Jhun Hua Chen, Hung-Chang Hsieh
  • Patent number: 9805154
    Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and inserting a first plurality of scattering bars in the IC design layout to form a first circular pattern of scattering bars around the first main feature. The first main feature is positioned at a center portion of the first circular pattern of scattering bars.
    Type: Grant
    Filed: May 15, 2015
    Date of Patent: October 31, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Irene Ho, Ai-Jen Hung, Hung-Chang Hsieh, Kuei-Liang Lu, Ya Hui Chang
  • Patent number: 9799567
    Abstract: A method of fabricating a semiconductor device is disclosed. The method includes forming a gate structure over a substrate. The gate structure includes a first hard mask layer. The method also includes forming a source/drain (S/D) feature in the substrate adjacent to the gate structure, forming a sidewall spacer along sidewalls of the gate structure. The sidewall spacer has an outer edge at its upper portion facing away from the gate structure. The method also includes forming a second spacer along sidewalls of the gate structure and along the outer edge of the sidewall spacer, forming dielectric layers over the gate structure, forming a trench extending through the dielectric layers to expose the source/drain feature while the gate structure is protected by the first hard mask layer and the sidewall spacer with the second spacer. The method also includes forming a contact feature in the trench.
    Type: Grant
    Filed: October 23, 2014
    Date of Patent: October 24, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Ming-Jhih Kuo, Yu-Hsien Lin, Hung-Chang Hsieh, Jhun Hua Chen
  • Patent number: 9791775
    Abstract: A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.
    Type: Grant
    Filed: March 11, 2016
    Date of Patent: October 17, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chun-Wei Chang, Hong-Da Lin, Chih-Chien Wang, Chun-Chang Chen, Wang-Pen Mo, Hung-Chang Hsieh
  • Patent number: 9754478
    Abstract: Reducing nuisance notifications from building automation systems is described herein. One device includes a memory, and a processor configured to execute executable instructions stored in the memory to receive a notification of an alarm from a building automation system, compare attributes of the alarm to attributes of alarms included in a database of suppressed alarms, refrain from transmitting a notification of the alarm to a mobile device in response to the attributes of the alarm matching attributes of any of the alarms in the database, and transmit a notification of the alarm to a mobile device in response to the attributes of the alarm not matching the attributes of any of the alarms in the database.
    Type: Grant
    Filed: May 31, 2016
    Date of Patent: September 5, 2017
    Assignee: Honeywell International Inc.
    Inventors: Gary Fuller, Dae-Soon Kwon, Yi-Chang Hsieh, Andie Kurniawan, Martin Lee, Paul Vanderstraeten
  • Patent number: 9741541
    Abstract: A high frequency plasma apparatus includes a reaction chamber, a first electrode, a second electrode, and a plurality of feed points located at one of the two electrodes at least. The feed points are used to simultaneously generate a first standing wave and a second standing wave, with different temporal and spatial patterns. By adjusting amplitudes of the two standing waves and the temporal and spatial phase differences between the two standing waves appropriately, plasma uniformity of the high frequency plasma apparatus can be effectively improved.
    Type: Grant
    Filed: June 29, 2016
    Date of Patent: August 22, 2017
    Assignee: INSTITUTE OF NUCLEAR ENERGY RESEARCH, ATOMIC ENERGY COUNCIL, EXECUTIVE YUAN, R.O.C.
    Inventors: Hsin-Liang Chen, Cheng-Chang Hsieh, Deng-Lain Lin, Ching-Pei Tseng, Ming-Chung Yang
  • Patent number: 9741600
    Abstract: An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with upper, intermediate and lower portions of increasing diameter. A hollow edge ring rests on the intermediate edge portion and a substrate disposed on the rotatable disc is lifted and transported by robot blades positioned beneath the edge ring and which lift the edge ring which holds the substrate around its edges. The rotatable disc and edge ring find application in MOCVD and other semiconductor manufacturing tools.
    Type: Grant
    Filed: June 7, 2016
    Date of Patent: August 22, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chih-Chang Hsieh, Chung-chieh Hsu, Chian-kun Chan, Chih-Kuo Chang, Chih-Ping Chen, Hsu-Shui Liu, Kai Lo, Wei-ting Hsiao, Yung-Kai Lin
  • Patent number: 9735476
    Abstract: The present invention discloses an antenna apparatus. The antenna apparatus includes a first antenna array and a second antenna array. The first antenna array includes multiple first radiating elements for transmitting radio signals of a first frequency. The second antenna array includes multiple second radiating elements for transmitting radio signals of a second frequency, wherein the first and second radiating elements are arranged in a staggered manner; wherein each of the first radiating elements is disposed between two of the second radiating elements; and wherein each of the second radiating elements is disposed between two of the first radiating elements.
    Type: Grant
    Filed: August 5, 2015
    Date of Patent: August 15, 2017
    Assignee: ACCTON TECHNOLOGY CORPORATION
    Inventors: I-Ru Liu, Chih-Chang Hsieh, Yi-Chang Chen, Yang-Te Fu, Chang-Cheng Liu, Chun-Teng Hsu
  • Publication number: 20170211668
    Abstract: An armlike driving mechanism includes a power source connected to a screw rod and a nut, a driving assembly including a first gear, a second gear, and a drive belt, a rail assembly including a linear rail and a sliding element, and a connecting block fixed on the drive belt and linked to the nut and the sliding element. The power source drives the screw rod and the nut by back and forth rotation, thereby displacing the sliding element in an X axle direction and driving the first gear in an Y axle direction by the connecting block and the drive belt, so as to operate the armlike driving mechanism.
    Type: Application
    Filed: January 27, 2016
    Publication date: July 27, 2017
    Inventor: TSUNG-CHANG HSIEH
  • Patent number: 9711367
    Abstract: The present disclosure provides a semiconductor fabrication method. The method includes modifying an edge portion of a wafer such that the edge portion are prevented from resist coating; coating a resist layer on the front surface of the wafer, wherein the resist layer is free from the edge portion of the wafer; and performing an exposing process to the resist layer.
    Type: Grant
    Filed: June 1, 2016
    Date of Patent: July 18, 2017
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hung-Chung Chien, Hung-Chang Hsieh, Jhun Hua Chen, Shu-Fang Chen
  • Publication number: 20170199498
    Abstract: The present disclosure discloses a timekeeping apparatus, comprising: a case; a display area on a side of the case; a light source near the display area, the light source being capable of emitting light with different colors to indicate different types of messages received by the timekeeping apparatus.
    Type: Application
    Filed: November 4, 2016
    Publication date: July 13, 2017
    Inventors: Chih-Chang HSIEH, Te-Hsiu CHIU, Ming-Yish CHEN
  • Patent number: 9703918
    Abstract: A method of optimizing a semiconductor mask layout is provided. The method includes accessing a digital file comprising the semiconductor mask layout, accessing processing condition parameters describing process conditions, receiving a request from a user of a mask layout system to initiate a semiconductor mask layout optimization process, applying a set of rules to insert an array of assist features into the semiconductor mask layout, and updating the digital file. The semiconductor mask layout includes a plurality of parallel mask features, wherein pairs of the parallel mask features share an end-to-end region between the parallel mask features of each pair, with an imaginary axis bisecting the end-to-end regions. Each assist feature is located proximate to at least one end-to-end region, and the imaginary axis intersects each assist feature. Related photomasks, design layout systems, and computer-readable media are also provided.
    Type: Grant
    Filed: March 16, 2015
    Date of Patent: July 11, 2017
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Wei-De Ho, Chi-Yuan Sun, Ya Hui Chang, Hung-Chang Hsieh
  • Publication number: 20170182315
    Abstract: A method for interferential current stimulation by complex active regions, in which the method is adapted to generate low frequency interference active regions formed of staggered electric flux lines by disposing electrodes to stimulate specific parts of a human body by supplying electricity is provided.
    Type: Application
    Filed: December 28, 2016
    Publication date: June 29, 2017
    Inventor: Kou-Chang Hsieh
  • Publication number: 20170176951
    Abstract: The present disclosure discloses a multi-eye analog smart timekeeping apparatus, comprising: a dial, comprising a dial substrate comprising a plurality of view regions; an arm positioned above the dial; a display panel positioned below the dial and comprising a plurality of display regions, each of the display regions corresponding to one of at least two of the view regions; and a shaft connected to the arm and being through the dial and the display panel. The present disclosure also discloses a method of making a display panel that may be used with the timekeeping apparatus, comprising: providing a first substrate comprising a first area; forming a display layer on the first substrate outside the first area; applying encapsulation material on the first area and around the display layer; sealing the display layer between the first substrate and a second substrate; and drilling a hole in the first area, wherein a size of the hole is smaller than a size of the first area.
    Type: Application
    Filed: December 21, 2015
    Publication date: June 22, 2017
    Inventors: Chih-Chang HSIEH, Te-Hsiu CHIU, Ming-Yish CHEN
  • Patent number: 9685233
    Abstract: A multiple bits per cell memory is operated by applying a one-pass, multiple-level programming, using a single pulse sequence one time (or in one-pass), such as an incremental pulse program sequence, with program verify steps for multiple target program levels, to program multiple bits per cell in a plurality of memory cells. Using these techniques, the number of program pulses required, and the time required for programming the data can be reduced. As a result, an improvement in programming throughput and a reduction in disturbance conditions are achieved. Variants of the one-pass, multiple-level programming operation can be adopted for a variety of memory cell types, memory architectures, programming speeds, and data storage densities.
    Type: Grant
    Filed: January 13, 2014
    Date of Patent: June 20, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Chang Hsieh, Ti-Wen Chen, Yung Chun Li, Kuo-Pin Chang
  • Patent number: 9672920
    Abstract: This disclosure provides a memory device. The memory device includes a plurality of memory cells and a control circuit coupled to the memory cells. The control circuit is configured to provide a first programming voltage to the memory cells; verify the memory cells against an interim level verify voltage to divide the memory cells into a first group of memory cells and a second group of memory cells according to whether the memory cells do not reach or do reach the interim level verify voltage, respectively; provide a second programming voltage to the first group of memory cells and inhibit the second group of memory cells from receiving the second programming voltage, the second programming voltage being greater than or equal to the first programming voltage; and verify the first group of memory cells and the second group of memory cells against a desired level voltage.
    Type: Grant
    Filed: March 13, 2015
    Date of Patent: June 6, 2017
    Assignee: Macronix International Co., Ltd.
    Inventors: Chih-Chang Hsieh, Ti Wen Chen, Yungchun Li, Hang Ting Lue
  • Patent number: 9651869
    Abstract: A method for preparing a wafer includes forming a film layer on a substrate of the wafer; coating the film layer with a photoresist layer; exposing a first portion of the photoresist layer to a beam of light; and patterning a second portion of the photoresist layer after performing exposing the first portion of the photoresist layer. A cross-link reaction is caused on the first portion of the photoresist layer and the first portion of the photoresist layer is converted to a reacted first portion of the photoresist layer. The reacted first portion of the photoresist layer is near an edge of the wafer. The second portion of the photoresist layer is different from the reacted first portion of the photoresist layer. The second portion of the photoresist layer is converted to a patterned second portion of the photoresist layer.
    Type: Grant
    Filed: April 7, 2015
    Date of Patent: May 16, 2017
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Chun-Wei Chang, Wang-Pen Mo, Hung-Chang Hsieh
  • Patent number: 9619124
    Abstract: Described herein are frameworks, devices and methods configured for enabling display for facility information and content, in some cases via touch/gesture controlled interfaces. Embodiments of the invention have been particularly developed for allowing an operator to conveniently access a wide range of information relating to a facility via, for example, one or more wall mounted displays. While some embodiments will be described herein with particular reference to that application, it will be appreciated that the invention is not limited to such a field of use, and is applicable in broader contexts.
    Type: Grant
    Filed: June 9, 2014
    Date of Patent: April 11, 2017
    Assignee: Honeywell International Inc.
    Inventors: John D. Morrison, Graeme Laycock, Yi-Chang Hsieh