Abstract: A device for semiconductor fabrication includes a substrate and a layer formed over the substrate, wherein the layer includes an alignment mark. The alignment mark includes a first plurality of elongated members that are oriented lengthwise along a first direction and are distributed along a second direction. The alignment mark further includes a second plurality of elongated members that are oriented lengthwise along a third direction perpendicular to the first direction and are distributed along the second direction, wherein the second direction is different from each of the first and third directions.

Abstract: The present invention relates to a roll-to-roll hybrid plasma modular coating system, which comprises: at least one arc plasma processing unit, at least one magnetron sputtering plasma processing unit, a metallic film and at least one substrate feeding unit. Each of the arc plasma processing unit is formed with a first chamber and an arc plasma source. Each of the magnetron sputtering plasma processing unit is formed with a second chamber and at least one magnetron sputtering plasma source. The metallic film is disposed in the arc plasma processing unit to avoid chamber wall being deposited by the arc plasma source; There are at least one arc plasma processing unit, at least one magnetron sputtering plasma processing unit and at least one winding/unwinding unit connected in series to lay at least one thin layer by arc plasma deposition or by magnetron sputtering plasma onto substrate material.

Abstract: A composite powder is provided. The composite powder comprises 80-97 wt % of carbide and 3-20 wt % of blending metal powder comprising cobalt and a first metal powder, wherein the first metal powder is formed of one of aluminum, titanium, iron, nickel, or a combination thereof, and the amount of cobalt is 90-99% of total blending metal powder.

Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

Abstract: A method includes receiving information defining at least one condition and at least one action associated with a rule. Each condition is associated with an event in an industrial process control and automation system, and each action is associated with information related to the event. The method also includes, based on actual events in the industrial process control and automation system, generating one or more notifications for one or more users of one or more mobile devices using the rule. The method further includes transmitting the one or more notifications for delivery to the one or more mobile devices.

Abstract: The present disclosure provides one embodiment of an IC method that includes receiving an IC design layout including a first main feature and inserting a first plurality of scattering bars in the IC design layout to form a first circular pattern of scattering bars around the first main feature. The first main feature is positioned at a center portion of the first circular pattern of scattering bars.

Abstract: An ultraviolet curing apparatus includes a chamber, a gas flow generator, and an ultraviolet lamp. The gas flow generator includes a top liner and a bottom liner coupled to each other. The top liner and the bottom liner are disposed in the chamber, and are made of low-coefficient of thermal expansion material. The ultraviolet lamp is disposed on the chamber and is configured for providing ultraviolet light.

Abstract: A probe card for use in testing a wafer and a method of making the probe card include a printed circuit board (PCB) formed with a conductor pattern and a probe head in proximity to the PCB, the probe head defining at least one hole through the probe head, and the probe head being made of an electrically insulating material. At least one conductive pogo pin is disposed respectively in the at least one hole, the pogo pin having a first end electrically connected to the conductor pattern on the PCB. At least one conductive probe pin includes a cantilever portion and a tip portion. The cantilever portion is in contact with and electrically connected to a second end of the pogo pin, and the tip portion is electrically connectable to the wafer to electrically connect the wafer to the conductor pattern on the PCB. The cantilever portion of the probe pin is fixedly attached to the probe head.

Abstract: A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.

Abstract: A method of forming a target pattern includes forming a first trench in a substrate with a cut mask; forming a first plurality of lines over the substrate with a first main mask, wherein the first main mask includes at least one line that overlaps the first trench and is thereby cut into at least two lines by the first trench; forming a spacer layer over the substrate and the first plurality of lines and over sidewalls of the first plurality of lines; forming a patterned material layer over the spacer layer with a second main mask thereby the patterned material layer and the spacer layer collectively define a second plurality of trenches; removing at least a portion of the spacer layer to expose the first plurality of lines; and removing the first plurality of lines thereby resulting a patterned spacer layer over the substrate.

Abstract: A memory device and an erase method for the memory device are provided. The memory device includes plural blocks and a controller. The plural blocks include at least one first block and at least one second block. The erase method is controlled by the controller and includes the following steps. A first stage erase operation and a second stage erase operation are sequentially performed on the at least one first block in a first time interval and a second time interval. The first stage erase operation and the second stage erase operation are sequentially performed on the at least one second block in the second time interval and a third time interval.

Abstract: A method of optimizing a semiconductor mask layout is provided. The method includes accessing a digital file comprising the semiconductor mask layout, accessing processing condition parameters describing process conditions, receiving a request from a user of a mask layout system to initiate a semiconductor mask layout optimization process, applying a set of rules to insert an array of assist features into the semiconductor mask layout, and updating the digital file. The semiconductor mask layout includes a plurality of parallel mask features, wherein pairs of the parallel mask features share an end-to-end region between the parallel mask features of each pair, with an imaginary axis bisecting the end-to-end regions. Each assist feature is located proximate to at least one end-to-end region, and the imaginary axis intersects each assist feature. Related photomasks, design layout systems, and computer-readable media are also provided.

Abstract: This disclosure provides a memory device. The memory device includes a plurality of memory cells and a control circuit coupled to the memory cells. The control circuit is configured to provide a first programming voltage to the memory cells; verify the memory cells against an interim level verify voltage to divide the memory cells into a first group of memory cells and a second group of memory cells according to whether the memory cells do not reach or do reach the interim level verify voltage, respectively; provide a second programming voltage to the first group of memory cells and inhibit the second group of memory cells from receiving the second programming voltage, the second programming voltage being greater than or equal to the first programming voltage; and verify the first group of memory cells and the second group of memory cells against a desired level voltage.

Abstract: A method of fabricating a fin-like field-effect transistor (FinFET) device includes providing a substrate having a first region and a second region, and forming a plurality of mandrel features in the first region with a first spacing. The method further includes forming first spacers along sidewalls of the mandrel features with a targeted width A, and forming second spacers with a first width W1 along sidewalls of the first spacers, wherein two back-to-back adjacent second spacers are separated by a gap. The method further includes depositing a dielectric material in the gap and in the second region, and performing a first cut thereby removing a first subset of the first spacers. Coincident with the removing of the first subset, the method further includes partially removing the dielectric material in the second region thereby forming a mesa of the dielectric material in the second region.

Abstract: A method of fabricating a fin-like field-effect transistor device is disclosed. The method includes forming mandrel features over a substrate and performing a first cut to remove mandrel features to form a first space. The method also includes performing a second cut to remove a portion of mandrel features to form a line-end and an end-to-end space. After the first and the second cuts, the substrate is etched using the mandrel features, with the first space and the end-to-end space as an etch mask, to form fins. Depositing a space layer to fully fill in a space between adjacent fins and cover sidewalls of the fins adjacent to the first space and the end-to-end space. The spacer layer is etched to form sidewall spacers on the fins adjacent to the first space and the end-to-end space and an isolation trench is formed in the first space and the end-to-end space.

Abstract: An apparatus and method for processing semiconductor substrates provides a substrate stage being a rotatable disc with a solid surface and a terraced edge with upper, intermediate and lower portions of increasing diameter. A hollow edge ring rests on the intermediate edge portion and a substrate disposed on the rotatable disc is lifted and transported by robot blades positioned beneath the edge ring and which lift the edge ring which holds the substrate around its edges. The rotatable disc and edge ring find application in MOCVD and other semiconductor manufacturing tools.

Abstract: A water-repellent earphone is formed of a main body and a water-repellent breathable member. The main body includes a receiving space for accommodating a speaker. The speaker partitions the receiving space to make a rear chamber. The main body includes a drainage tunnel communication with a first opening and a second opening, both of which are located on an external surface of the main body. The main body further includes a venthole communicating with the drainage tunnel and the rear chamber. The water-repellent breathable member is formed and located at the venthole. In light of the structure mentioned above, the drainage tunnel can help the earphone quickly expel the moisture to prevent the moisture from damage to the speaker and to boost the frequency response and acoustic performance within the low-frequency range.

Abstract: A method provides an integrated circuit (IC) substrate having first and second alignment marks defined in a first pattern layer, and third and fourth alignment marks defined in a second pattern layer. The first and second alignment marks are illuminated, through a photomask, with a first light to determine a first layer alignment error including a first alignment error and a second alignment error. The first alignment error has more weight than the second alignment error in determining the first layer alignment error. The third and fourth alignment marks are illuminated with a second light to determine a second layer alignment error including a third alignment error in relation to the third alignment mark and a fourth alignment error in relation to the fourth alignment mark. The third alignment error has more weight than the fourth alignment error in determining the second layer alignment error.

Abstract: A method includes forming a first photo resist layer over a base structure and a target feature over the base structure, performing an un-patterned exposure on the first photo resist layer, and developing the first photo resist layer. After the step of developing, a corner portion of the first photo resist layer remains at a corner between a top surface of the base structure and an edge of the target feature. A second photo resist layer is formed over the target feature, the base structure, and the corner portion of the first photo resist layer. The second photo resist layer is exposed using a patterned lithography mask. The second photo resist layer is patterned to form a patterned photo resist.

Abstract: A film layer on a substrate of the wafer is patterned to form a first plurality of areas of the film layer and a second plurality of areas of the film layer. The first plurality of areas of the film layer is removed. The second plurality of areas of the film layer is kept on the substrate. A first portion of the film layer is kept on the substrate. A first edge of the first portion of the film layer is substantially near an edge of the wafer. The first portion of the film layer defines a boundary for the wafer.