Patents by Inventor Chang Huang

Chang Huang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20250244186
    Abstract: A torque sensing bottom bracket includes a bottom bracket sensor assembly that detects torque applied thereto and generates an analog torque signal, and a signal processor that receives the analog torque signal and generates a digital torque signal. The signal processor is configured to receive the digital torque signal, to perform a format conversion on the digital torque signal, and to outputs a converted digital torque signal in a specific signal format. The signal processor is then configured to output the converted digital torque signal to an external back-end device.
    Type: Application
    Filed: May 21, 2024
    Publication date: July 31, 2025
    Inventors: FU-CHANG HUANG, YI-RU LU, CHUN-SHENG LEE
  • Patent number: 12374525
    Abstract: The method includes placing a wafer in a chamber body of a plasma processing tool; moving a first movable jig along an arc path to comb a spiral-shaped radio frequency (RF) coil over the chamber body, the first movable jig having a plurality of first confining slots penetrated by a plurality of coil segments of the spiral-shaped RF coil, respectively; and generating plasma in the chamber body through the spiral-shaped RF coil.
    Type: Grant
    Filed: March 7, 2022
    Date of Patent: July 29, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Yung Chang Huang, Chia Jung Hsu, Yu Hsiu Chen
  • Publication number: 20250233119
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Application
    Filed: April 1, 2025
    Publication date: July 17, 2025
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Patent number: 12352362
    Abstract: A bi-directional inflating tool includes a handle assembly having an inner tube, an outer tube movably sleeved onto the inner tube and a sleeve pushing and pulling member with a sleeve pushing portion and a sleeve pulling portion, an adapter assembly connected to the inner tube, two nozzle connectors connected to the adapter assembly, two moving control sleeves sleeved onto the nozzle connectors respectively and each having an abutted moving portion, which are respectively pushed by the sleeve pushing portion and pulled by the sleeve pulling portion to displace axially, two detent assemblies controlled by the moving control sleeves respectively for engagement with the gas nozzle, and two valve assemblies controlling the communication of the adapter assembly with the nozzle connectors respectively for aeration. The moving control sleeves are operated separately, bringing simpleness and effort-saving, solving the time-consuming and laborious problem of the conventional bi-directional inflating tool.
    Type: Grant
    Filed: February 16, 2024
    Date of Patent: July 8, 2025
    Assignee: JIN DAI AUTO SUPPLIES CO., LTD.
    Inventor: Yen-Chang Huang
  • Publication number: 20250215292
    Abstract: An adhesive and multilayer structure are provided. The adhesive includes a polyimide, wherein the polyimide is a reaction product of a reactant (a) and a reactant (b). The reactant (a) is a first diamine or the reactant (a) includes of a first diamine and a second diamine, and the reactant (b) includes of a first dianhydride and a second dianhydride. The first diamine is a diphenyl-ether-moiety-containing diamine, the first dianhydride is a diphenyl-ether-moiety-containing dianhydride, the second diamine is not a diphenyl-ether-moiety-containing diamine, and the second dianhydride is not a diphenyl-ether-moiety-containing dianhydride. The total weight percentage of the first diamine and the first dianhydride is 55 wt % to 94 wt %, based on the total weight of the reactant (a) and the reactant (b).
    Type: Application
    Filed: August 21, 2024
    Publication date: July 3, 2025
    Applicant: INDUSTRIAL TECHNOLOGY RESEARCH INSTITUTE
    Inventors: Jauder Jeng, Yuan-Chang Huang, Kuan-Wei Chen, Jheng-Ying Li
  • Publication number: 20250216633
    Abstract: An optical fiber connection base is provided, including a socket, a light emitting module, and an optical fiber bundle. The socket has an extension portion and a base having an accommodating space. The base is provided with an insertion hole and an alignment hole that are spatially communicated with each other. A first direction extends along the insertion hole. A side surface of the light emitting element of the light emitting module corresponds to the insertion hole, defining a light emitting surface. One end of the optical fiber bundle is inserted into the insertion hole in the first direction, such that a light receiving end is defined. The light receiving end is adjacent to the light emitting surface, and a center of a cross section of the light receiving end corresponds to a center of the light emitting surface.
    Type: Application
    Filed: May 29, 2024
    Publication date: July 3, 2025
    Applicant: CLEVO CO.
    Inventors: Chien-Liang CHEN, Wei-Cheng LI, Hung-Chang HUANG
  • Patent number: 12347817
    Abstract: A semiconductor device package and a method of forming the same are provided. The semiconductor device package includes a package substrate having a first surface and a second surface opposite to the first surface. Several integrated devices are bonded to the first surface of the package substrate. A first underfill element is disposed over the first surface and surrounds the integrated devices. A first molding layer is disposed over the first surface and surrounds the integrated devices and the first underfill element. A semiconductor die is bonded to the second surface of the package substrate. A second underfill element is disposed over the second surface and surrounds the semiconductor die. A second molding layer is disposed over the second surface and surrounds the semiconductor die and the second underfill element. Several conductive bumps are disposed over the second surface and adjacent to the second molding layer.
    Type: Grant
    Filed: January 9, 2024
    Date of Patent: July 1, 2025
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Heh-Chang Huang, Fu-Jen Li, Pei-Haw Tsao, Shyue-Ter Leu
  • Publication number: 20250210536
    Abstract: A chip package structure includes a first chip structure having a first substrate and a first interconnect layer over the first substrate and a second chip structure over the first interconnect layer. The chip package structure also includes a conductive pillar over the first interconnect layer and a molding layer over the first interconnect layer, the first chip structure, the second chip structure, and the conductive pillar. The chip package structure further includes a conductive bump embedded in the molding layer and over a top surface of the conductive pillar. A portion of the molding layer is between the conductive bump and a peripheral portion of the top surface of the conductive pillar. The conductive bump extends to a central portion of the top surface of the conductive pillar. The portion of the molding layer tapers toward the central portion of the top surface of the conductive pillar.
    Type: Application
    Filed: March 10, 2025
    Publication date: June 26, 2025
    Applicant: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Heh-Chang HUANG, Fu-Jen LI, Pei-Haw TSAO, Shyue-Ter LEU
  • Publication number: 20250201604
    Abstract: A method includes carrying a wafer by using a fork of a delivering robot of an annealing apparatus; placing the wafer, by using the fork, onto a top surface of a cooling plate of the annealing apparatus; during placing the wafer, sensing, by a sensor of the annealing apparatus, a vibration of the wafer; and controlling, by a circuitry of the annealing apparatus, a motion of the fork according to the vibration of the wafer sensed by the sensor.
    Type: Application
    Filed: March 3, 2025
    Publication date: June 19, 2025
    Applicant: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
    Inventors: Yung-Chang HUANG, Yu-Chi TSAI
  • Patent number: 12334920
    Abstract: A level shifter includes a level shifting circuit and a voltage tracking circuit. The level shifting circuit receives an input signal through an input terminal and converts the input signal from a first power domain to a second power domain to generate an output signal at an output terminal. The voltage tracking circuit is coupled to first and second voltage terminals, and tracks one with a lower level among voltages of the first and second voltage terminals to generate a control voltage. The level shifting circuit includes first and second N-type transistors. The first N-type transistor has a gate coupled to the input terminal, a drain coupled to a first node, and a source coupled to a ground. The second N-type transistor has a gate receiving the control voltage, a drain coupled to the output terminal at a second node, and a source coupled to the input terminal.
    Type: Grant
    Filed: November 22, 2023
    Date of Patent: June 17, 2025
    Assignee: VANGUARD INTERNATIONAL SEMICONDUCTOR CORPORATION
    Inventors: Jung-Tsun Chuang, Shao-Chang Huang, Li-Fan Chen, Chun-Chih Chen, Gong-Kai Lin, Chien-Wei Wang
  • Publication number: 20250189723
    Abstract: A method of fabricating a semiconductor device includes providing a substrate that includes a handle substrate, a bottom cladding layer, and a semiconductor layer stacked in sequence from bottom to top. The substrate includes an electronic integrated circuit (EIC) region and a photonic integrated circuit (PIC) region. A thermal oxidation process is performed on the semiconductor layer in the PIC region to form an oxide layer. A first thickness of the semiconductor layer in the EIC region is greater than a second thickness of the semiconductor layer below the oxide layer. The oxide layer is removed and a PIC structure is formed on the bottom cladding layer in the PIC region. An EIC structure is formed on the bottom cladding layer in the EIC region. An interconnect structure is formed to be electrically connected to the PIC and EIC structures.
    Type: Application
    Filed: December 8, 2023
    Publication date: June 12, 2025
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Ming-Cheng Lo, Shih-Chang Huang, Jui-Chun Chang, Wu-Hsi Lu, Yu-Che Tsai, Shih-Hao Liu, Yen-Shih Ho
  • Patent number: 12325541
    Abstract: An unmanned aerial vehicle (UAV) includes a fuselage, a power driving unit, and an UAV arm. The UAV arm includes a cantilever, a mounting base, and a connecting portion. The mounting base is connected to a first end of the cantilever. The mounting base is configured for a power driving unit of the UAV to be mounted. The connecting portion is connected to a second end of the cantilever. The connecting portion is configured to be connected to the fuselage of the UAV. An upper end of a cross section of the cantilever is arc-shaped, and a lower end of the cross section of the cantilever is pointed. The cross section of the cantilever is a section perpendicular to a direction from the first end of the cantilever toward the second end of the cantilever.
    Type: Grant
    Filed: July 12, 2023
    Date of Patent: June 10, 2025
    Assignee: AUTEL ROBOTICS CO., LTD.
    Inventor: Chang Huang
  • Patent number: 12325490
    Abstract: A wheel hub motor includes a shaft, a stator unit and a rotating unit. The stator unit includes a coreless stator set. The rotating unit includes a rotating seat set sleeved on the shaft, a bearing set, and two rotor sets fixedly mounted to the rotating seat set. The rotating seat set defines a bearing mounting space adjacent to the shaft and receiving the bearing set therein, and a rotor space radially spaced apart from the bearing mounting space and receiving the rotor sets therein. The coreless stator set is disposed between the rotor sets such that, when being energized to generate a magnetic field, the rotor sets rotate about the shaft so as to drive the rotating seat set and the bearing set to rotate.
    Type: Grant
    Filed: August 19, 2022
    Date of Patent: June 10, 2025
    Assignee: MOTEK AUTOMATION CO., LTD.
    Inventor: Fu-Chang Huang
  • Publication number: 20250159336
    Abstract: A method for a camera system includes generating, by a processor, a set of control parameters for an image sensor to capture a first image frame. The set of control parameters correspond to at least one capture setting. The method further includes determining, by the processor, whether a change in the at least one capture setting has occurred since capturing the first image frame. A first subsequent image frame is captured using the set of control parameters for the first image frame when no change in the at least one capture setting has occurred.
    Type: Application
    Filed: November 15, 2024
    Publication date: May 15, 2025
    Inventors: Chi-Cheng Ju, Yan-Shao Liu, Yu-Chang Huang, Chih-Hung Wu
  • Publication number: 20250155630
    Abstract: A backlight module includes a light guide plate, a light source, and an optical film. The light guide plate has a light incident surface and a light exiting surface opposite to the light incident surface, in which the light exiting surface has a normal line. The light source is adjacent to the light incident surface. The optical film is disposed to the light exiting surface and includes plural parallel prisms and plural microstructures. An extending direction of each of the prisms is perpendicular to the normal line, and each of the prisms faces the light exiting surface of the light guide plate. Each of the microstructures is located on a surface of the optical film which faces away from the light guide plate. Each of the microstructures has a pyramid structure with plural facets. The prisms are located between the microstructures and the light exiting surface.
    Type: Application
    Filed: January 17, 2025
    Publication date: May 15, 2025
    Inventors: Chia-Yin CHANG, Po-Chang HUANG, Kun-Cheng LIN
  • Publication number: 20250159341
    Abstract: A method of operating an imaging apparatus includes generating combined sensor settings for a plurality of image sensors by an image signal processor (ISP), and transmitting the combined sensor settings from the ISP in a single operation. The ISP includes a single software flow control for the plurality of image sensors. The method significantly optimizes CPU usage and reduces power consumption in multi-sensor camera systems. By consolidating multiple software and data control flows into a single, unified process, the system achieves a substantial reduction in computational overhead.
    Type: Application
    Filed: November 8, 2024
    Publication date: May 15, 2025
    Applicant: MEDIATEK INC.
    Inventors: Chi-Cheng Ju, Yan-Shao Liu, Yu-Chang Huang, Yu-En Wu
  • Patent number: 12294002
    Abstract: An integrated circuit package and a method of forming the same are provided. The method includes attaching an integrated circuit die to a first substrate. A dummy die is formed. The dummy die is attached to the first substrate adjacent the integrated circuit die. An encapsulant is formed over the first substrate and surrounding the dummy die and the integrated circuit die. The encapsulant, the dummy die and the integrated circuit die are planarized, a topmost surface of the encapsulant being substantially level with a topmost surface of the dummy die and a topmost surface of the integrated circuit die. An interior portion of the dummy die is removed. A remaining portion of the dummy die forms an annular structure.
    Type: Grant
    Filed: May 15, 2024
    Date of Patent: May 6, 2025
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Shang-Yun Hou, Sung-Hui Huang, Kuan-Yu Huang, Hsien-Pin Hu, Yushun Lin, Heh-Chang Huang, Hsing-Kuo Hsia, Chih-Chieh Hung, Ying-Ching Shih, Chin-Fu Kao, Wen-Hsin Wei, Li-Chung Kuo, Chi-Hsi Wu, Chen-Hua Yu
  • Publication number: 20250137543
    Abstract: A bi-directional inflating tool includes a handle assembly having an inner tube, an outer tube movably sleeved onto the inner tube and a sleeve pushing and pulling member with a sleeve pushing portion and a sleeve pulling portion, an adapter assembly connected to the inner tube, two nozzle connectors connected to the adapter assembly, two moving control sleeves sleeved onto the nozzle connectors respectively and each having an abutted moving portion, which are respectively pushed by the sleeve pushing portion and pulled by the sleeve pulling portion to displace axially, two detent assemblies controlled by the moving control sleeves respectively for engagement with the gas nozzle, and two valve assemblies controlling the communication of the adapter assembly with the nozzle connectors respectively for aeration. The moving control sleeves are operated separately, bringing simpleness and effort-saving, solving the time-consuming and laborious problem of the conventional bi-directional inflating tool.
    Type: Application
    Filed: February 16, 2024
    Publication date: May 1, 2025
    Inventor: Yen-Chang HUANG
  • Publication number: 20250141220
    Abstract: An ESD protection circuit is coupled to a first pad and includes an ESD detection circuit, a P-type transistor, an N-type transistor, and a discharge circuit. The ESD detection circuit determines whether an ESD event occurs on the first pad to generate a detection signal at a first node. The P-type transistor comprises a source coupled to the first pad, a drain coupled to a second node, and a gate coupled to the first node. The N-type transistor comprises a drain coupled to the second node, a source coupled to a ground, and a gate coupled to a second pad. The discharge circuit is coupled between the first pad and the ground and controlled by a driving signal at the second node. When the ESD protection circuit is in an operation mode, the first pad receives a first voltage, and a second pad receives a second voltage.
    Type: Application
    Filed: November 1, 2023
    Publication date: May 1, 2025
    Applicant: Vanguard International Semiconductor Corporation
    Inventors: Chih-Hsuan LIN, Shao-Chang HUANG, Yeh-Ning JOU, Chieh-Yao CHUANG, Hwa-Chyi CHIOU, Wen-Hsin LIN, Kai-Chieh HSU, Ting-Yu CHANG, Hsien-Feng LIAO
  • Patent number: D1073666
    Type: Grant
    Filed: September 4, 2023
    Date of Patent: May 6, 2025
    Assignee: Shenzhen Jiteng Network Technology Co., Ltd.
    Inventor: Chang'e Huang