Abstract: A method of manufacturing a floating gate provides an enhancement for the efficiencies of electron charge and injection. First, a conductive pattern, constituting the floating gate is formed on a substrate. A first insulation layer is formed on a sidewall of the conductive pattern, and then a second insulation layer is formed at an upper portion of the conductive pattern in ways that increase the sharpness of an edge portion where the sidewall and upper portions of the conductive pattern meet. Therefore, electron transference from the floating ate to a control gate is facilitated.

Abstract: A method of fabricating split gate type FLASH memory device comprises forming trench device isolation layers in a substrate to define a plurality of parallel first active regions. A gate insulation pattern, a conductive pattern and a hard mask pattern, which are sequentially stacked, are formed to have sidewalls aligned to sidewalls of the trench device isolation layer. Along each of the first active regions, the hard mask pattern is removed at regular intervals to expose a top of the conductive pattern. An oxide pattern is formed on the exposed top of the conductive pattern and the hard mask pattern is removed. Using the oxide pattern as an etch mask, the conductive pattern is etched to form floating gate patterns arranged over each of the first active regions at regular intervals. Tunnel oxide layers are formed on sidewalls of the floating gate patterns. A plurality of control gate electrodes are formed to cross over the first active regions.

Abstract: A method of manufacturing a floating gate provides an enhancement for the efficiencies of electron discharge and injection. First, a conductive pattern, constituting the arefloating gateforeon, is formed on a substrate. A first insulation layer is formed on a sidewall of the conductive pattern, and then a second insulation layer is formed at an upper portion of the conductive pattern in ways that each increase the sharpness of an edge portion where the sidewall and upper portions of the conductive pattern meet. Therefore, electron transference from the floating gate to a control gate is facilitated.

Abstract: A method of fabricating split gate type FLASH memory device comprises forming trench device isolation layers in a substrate to define a plurality of parallel first active regions. A gate insulation pattern, a conductive pattern and a hard mask pattern, which are sequentially stacked, are formed to have sidewalls aligned to sidewalls of the trench device isolation layer. Along each of the first active regions, the hard mask pattern is removed at regular intervals to expose a top of the conductive pattern. An oxide pattern is formed on the exposed top of the conductive pattern and the hard mask pattern is removed. Using the oxide pattern as an etch mask, the conductive pattern is etched to form floating gate patterns arranged over each of the first active regions at regular intervals. Tunnel oxide layers are formed on sidewalls of the floating gate patterns. A plurality of control gate electrodes are formed to cross over the first active regions.