Patents by Inventor Chang-seok Kang

Chang-seok Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11508522
    Abstract: A multilayer electronic component include a first non-conductive resin layer, extending between a conductive resin layer and an electrode layer of a first external electrode, and a second non-conductive resin layer extending between a conductive resin layer and an electrode layer of a second external electrode. The first non-conductive layer and the second non-conductive layer may be spaced apart from each other to suppress arc discharge and to improve bending strength.
    Type: Grant
    Filed: April 24, 2020
    Date of Patent: November 22, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Seok Yi, Il Ro Lee, Chang Hak Choi, Bon Seok Koo, Jung Min Kim, Byung Woo Kang, San Kyeong
  • Publication number: 20220367560
    Abstract: Memory devices and methods of manufacturing memory devices are provided. The device and methods described decrease the resistivity of word lines by forming word lines comprising low resistivity materials. The low resistivity material has a resistivity in a range of from 5 ??cm to 100 ??cm. Low resistivity materials may be formed by recessing the word line and selectively growing the low resistivity materials in the recessed portion of the word line. Alternatively, low resistivity materials may be formed by depositing a metal layer and silicidating the metal in the word line region and in the common source line region.
    Type: Application
    Filed: May 11, 2022
    Publication date: November 17, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee
  • Publication number: 20220319601
    Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating word lines and dielectric material. There is at least one select-gate-for-drain (SGD) transistor in a first vertical hole extending through the memory stack, the select-gate-for-drain (SGD) transistor comprising a first gate material. At least one memory transistor is in a second vertical hole extending through the memory stack, the at least one memory transistor comprising a second gate material different from the first gate material.
    Type: Application
    Filed: March 28, 2022
    Publication date: October 6, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Qian Fu, Sung-Kwan Kang, Takehito Koshizawa, Fredrick Fishburn
  • Patent number: 11463035
    Abstract: A method of controlling a sensorless motor of an air compressor is provided to overcome the known problems of sensorless control methods and to improve control responsiveness. In various aspects of the present invention, a method of controlling a sensorless motor of an air compressor includes: performing a speed control for stopping a motor by a controller; determining a motor stopped state from an estimated motor speed while the speed control is performed by the controller; determining a rotor position estimated as a fixed position when the motor stopped state is determined by the controller; performing motor position control for moving the rotor position to the fixed position when the motor stopped state is determined; and starting sensorless control for driving the motor by setting the fixed position to an initial position when requesting a motor driving while the rotor position is maintained at the fixed position.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: October 4, 2022
    Assignees: Hyundai Motor Company, Kia Motors Corporation
    Inventors: Chang Seok You, Min Su Kang, Sung Do Kim, Dong Hun Lee
  • Publication number: 20220301783
    Abstract: A multilayer capacitor includes a capacitor body including a dielectric layer and a plurality of internal electrodes, and external electrodes disposed on both ends of the capacitor body and connected to exposed portions of the plurality of internal electrodes, respectively. Each of the external electrodes includes a conductive layer disposed on the capacitor body to be connected to one or more of the plurality of internal electrodes, a conductive resin layer covering the conductive layer, and including a plurality of metal particles, a plurality of elastic fine powder particles each having an elastic powder particle and a metal film plated on a surface of the elastic powder particle, and a conductive resin surrounding the plurality of metal particles and the plurality of elastic fine powder particles and contacting the conductive layer, and a plating layer covering the conductive resin layer.
    Type: Application
    Filed: June 9, 2022
    Publication date: September 22, 2022
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: San Kyeong, Chang Hak Choi, Jae Seok Yi, Bon Seok Koo, Jung Min Kim, Hae Sol Kang, Jun Hyeon Kim
  • Publication number: 20220285362
    Abstract: Methods for forming three-dimensional dynamic random-access memory (3D DRAM) structures that leverage a grid pattern of high aspect ratio holes to form subsequent features of the 3D DRAM. The method may include depositing alternating layers of crystalline silicon (c-Si) and crystalline silicon germanium (c-SiGe) using an heteroepitaxy process onto a substrate and HAR etching of a pattern of holes into the substrate. The holes configured to provide chemistry access to laterally etch or deposit materials to form 3D DRAM features without requiring subsequent HAR etching of holes to form the 3D DRAM features.
    Type: Application
    Filed: February 17, 2022
    Publication date: September 8, 2022
    Inventors: Fredrick David FISHBURN, Arvind KUMAR, Sony VARGHESE, Chang Seok KANG, Sung-Kwan KANG, Tomohiko KITAJIMA
  • Patent number: 11430801
    Abstract: Methods and apparatus for forming a plurality of nonvolatile memory cells are provided herein. In some embodiments, the method, for example, includes forming a plurality of nonvolatile memory cells, comprising forming, on a substrate, a stack of alternating layers of metal including a first layer of metal and a second layer of metal different from the first layer of metal; removing the first layer of metal to form spaces between the alternating layers of the second layer of metal; and one of depositing a first layer of material to partially fill the spaces to leave air gaps therein or depositing a second layer of material to fill the spaces.
    Type: Grant
    Filed: April 12, 2021
    Date of Patent: August 30, 2022
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Takehito Koshizawa, Mukund Srinivasan, Tomohiko Kitajima, Chang Seok Kang, Sung-Kwan Kang, Gill Y. Lee, Susmit Singha Roy
  • Publication number: 20220262571
    Abstract: A multilayer electronic component has a body and a non-conductive resin layer. The non-conductive resin layer includes a body cover portion disposed in a region of an external surface of the body in which an electrode layer of an external electrode is not disposed, and an extending portion extending from the body cover portion between the electrode layer and a conductive resin layer of the external electrode, to thereby suppress arc discharge, improve bending strength, and improve moisture resistance.
    Type: Application
    Filed: April 29, 2022
    Publication date: August 18, 2022
    Applicant: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Seok YI, Jung Min KIM, Bon Seok KOO, Chang Hak CHOI, Il Ro LEE, Byung Woo KANG, San KYEONG, Hae Sol KANG
  • Publication number: 20220262619
    Abstract: Methods of manufacturing memory devices are provided. The methods improve the quality of a selectively deposited silicon-containing dielectric layer. The method comprises selectively depositing a silicon-containing dielectric layer in a recessed region of a film stack. The selectively deposited silicon-containing dielectric layer is then exposed to a high-density plasma and annealed at a temperature greater than 800 ° C. to provide a silicon-containing dielectric film having a wet etch rate of less than 4 ?/min.
    Type: Application
    Filed: February 9, 2022
    Publication date: August 18, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Ning Li, Shuaidl Zhang, Mihaela A. Balseanu, Qi Gao, Rajesh Prasad, Tomohiko Kitajima, Chang Seok Kang, Deven Matthew Raj Mittal, Kyu-Ha Shim
  • Patent number: 11393630
    Abstract: A multilayer electronic component has a body and a non-conductive resin layer. The non-conductive resin layer includes a body cover portion disposed in a region of an external surface of the body in which an electrode layer of an external electrode is not disposed, and an extending portion extending from the body cover portion between the electrode layer and a conductive resin layer of the external electrode, to thereby suppress arc discharge, improve bending strength, and improve moisture resistance.
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Seok Yi, Jung Min Kim, Bon Seok Koo, Chang Hak Choi, Il Ro Lee, Byung Woo Kang, San Kyeong, Hae Sol Kang
  • Patent number: 11393633
    Abstract: A multilayer capacitor includes a capacitor body including a dielectric layer and a plurality of internal electrodes, and external electrodes disposed on both ends of the capacitor body and connected to exposed portions of the plurality of internal electrodes, respectively. Each of the external electrodes includes a conductive layer disposed on the capacitor body to be connected to one or more of the plurality of internal electrodes, a conductive resin layer covering the conductive layer, and including a plurality of metal particles, a plurality of elastic fine powder particles each having an elastic powder particle and a metal film plated on a surface of the elastic powder particle, and a conductive resin surrounding the plurality of metal particles and the plurality of elastic fine powder particles and contacting the conductive layer, and a plating layer covering the conductive resin layer.
    Type: Grant
    Filed: May 15, 2020
    Date of Patent: July 19, 2022
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: San Kyeong, Chang Hak Choi, Jae Seok Yi, Bon Seok Koo, Jung Min Kim, Hae Sol Kang, Jun Hyeon Kim
  • Publication number: 20220223616
    Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.
    Type: Application
    Filed: April 1, 2022
    Publication date: July 14, 2022
    Inventors: Chang Sup LEE, Phil Ouk NAM, Sung Yun LEE, Chang Seok KANG
  • Patent number: 11309326
    Abstract: A vertical semiconductor device including a plurality of interlayer insulating layer patterns spaced apart from each other on a substrate and stacked in a vertical direction; a plurality of conductive layer patterns arranged between the interlayer insulating layer patterns and each having a rounded end, wherein at least one of the conductive layer patterns is configured to extend from one side wall of each of the interlayer insulating layer patterns and include a pad region, and the pad region includes a raised pad portion configured to protrude from a surface of the at least one conductive layer pattern; an upper interlayer insulating layer to cover the interlayer insulating layer patterns and the conductive layer patterns; and a contact plug configured to penetrate the upper interlayer insulating layer to be in contact with the raised pad portion of the at least one conductive layer pattern.
    Type: Grant
    Filed: March 27, 2020
    Date of Patent: April 19, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Jo-young Park, Chang-seok Kang, Chang-sup Lee, Se-mee Jang
  • Publication number: 20220108728
    Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.
    Type: Application
    Filed: December 15, 2021
    Publication date: April 7, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
  • Patent number: 11296104
    Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.
    Type: Grant
    Filed: April 10, 2020
    Date of Patent: April 5, 2022
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
  • Patent number: 11295786
    Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.
    Type: Grant
    Filed: February 3, 2020
    Date of Patent: April 5, 2022
    Assignee: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
  • Publication number: 20220059555
    Abstract: Described is a memory string including at least one select gate for drain (SGD) transistor and at least one memory transistor in a vertical hole extending through a memory stack on a substrate. The memory stack comprises alternating non-replacement word lines and replacement insulators. A filled slit extends through the memory stack, and there are at least two select gate for drain (SGD) isolation regions in the memory stack adjacent the filled slit. A select-gate-for-drain (SGD) cut is patterned into the top few pairs of alternating layers in the memory stacks. Through the cut opening, the sacrificial layer of the memory stacks is removed, and an insulator layer is used to fill the opening.
    Type: Application
    Filed: August 11, 2021
    Publication date: February 24, 2022
    Applicant: Applied Material, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima
  • Publication number: 20220005810
    Abstract: Described are memory devices having stacked DRAM cells, resulting in an increase in DRAM cell bit-density. The area of a unit cell is composed of a capacitor, a cell transistor, an isolation region and a connection region, where every capacitor and active region for the cell capacitor is electrically isolated. The memory cells have supporting bars. Methods of forming a memory device are described. The methods include patterning the isolation region with supporting bars, removing non-insulator layers after isolation region patterning, and filling the opened region with an insulator.
    Type: Application
    Filed: June 22, 2021
    Publication date: January 6, 2022
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima
  • Publication number: 20210399011
    Abstract: Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.
    Type: Application
    Filed: June 14, 2021
    Publication date: December 23, 2021
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Mihaela A. Balseanu
  • Patent number: 11189635
    Abstract: Methods of manufacturing memory devices are provided. The methods decrease the thickness of the first layers and increase the thickness of the second layers. Semiconductor devices are described having a film stack comprising alternating nitride and second layers in a first portion of the device, the alternating nitride and second layers of the film stack having a nitride:oxide thickness ratio (Nf:Of); and a memory stack comprising alternating word line and second layers in a second portion of the device, the alternating word line and second layers of the memory stack having a word line:oxide thickness ratio (Wm:Om), wherein 0.1(Wm:Om)<Nf:Of<0.95(Wm:Om).
    Type: Grant
    Filed: March 30, 2020
    Date of Patent: November 30, 2021
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Mukund Srinivasan, Sanjay Natarajan