Patents by Inventor Chang-seok Kang

Chang-seok Kang has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20240098971
    Abstract: A memory cell array includes a plurality of memory levels stacked in a first direction, each of the plurality of memory levels including an active region, a cell transistor having a single gate above the active region in the first direction, and a cell capacitor having a bottom electrode layer that is electrically connected to the active region.
    Type: Application
    Filed: August 22, 2023
    Publication date: March 21, 2024
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok KANG, Sung-Kwan KANG
  • Patent number: 11935703
    Abstract: A multilayer electronic component has a body and a non-conductive resin layer. The non-conductive resin layer includes a body cover portion disposed in a region of an external surface of the body in which an electrode layer of an external electrode is not disposed, and an extending portion extending from the body cover portion between the electrode layer and a conductive resin layer of the external electrode, to thereby suppress arc discharge, improve bending strength, and improve moisture resistance.
    Type: Grant
    Filed: January 9, 2023
    Date of Patent: March 19, 2024
    Assignee: SAMSUNG ELECTRO-MECHANICS CO., LTD.
    Inventors: Jae Seok Yi, Jung Min Kim, Bon Seok Koo, Chang Hak Choi, Il Ro Lee, Byung Woo Kang, San Kyeong, Hae Sol Kang
  • Publication number: 20240090213
    Abstract: A method of forming a semiconductor memory device includes simultaneously filling a top portion of a first high aspect ratio (HAR) structure and a top portion a second HAR structure with a silicon-containing sacrificial layer by a cycle of a deposition process and an etch process, wherein the first HAR structure has a critical dimension (CD) of between 150 nm and 250 nm, and the second HAR structure has a CD of between 250 nm and 400 nm.
    Type: Application
    Filed: August 28, 2023
    Publication date: March 14, 2024
    Inventors: Jialiang WANG, Soonil LEE, Eswaranand VENKATASUBRAMANIAN, Chang Seok KANG, Sanjay G. KAMATH, Abhijit B. MALLICK, Srinivas GUGGILLA, Amy CHILD, Sung-Kwan KANG, Balasubramanian PRANATHARTHIHARAN
  • Patent number: 11930637
    Abstract: Described is selective deposition of a silicon nitride (SiN) trap layer to form a memory device. A sacrificial layer is used for selective deposition in order to permit selective trap deposition. The trap layer is formed by deposition of a mold including a sacrificial layer, memory hole (MH) patterning, sacrificial layer recess from MH side, forming a deposition-enabling layer (DEL) on a side of the recess, and selective deposition of trap layer. After removing the sacrificial layer from a slit pattern opening, the deposition-enabling layer (DEL) is converted into an oxide to be used as blocking oxide.
    Type: Grant
    Filed: June 14, 2021
    Date of Patent: March 12, 2024
    Assignee: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Mihaela A. Balseanu
  • Patent number: 11910614
    Abstract: A three-dimensional semiconductor device and a method of forming the same are provided. The three-dimensional semiconductor device comprises a substrate including first and second areas; first and second main separation patterns, disposed on the substrate and intersecting the first and second areas; gate electrodes disposed between the first and second main separation patterns and forming a stacked gate group, the gate electrodes sequentially stacked on the first area and extending in a direction from the first area to the second area; and at least one secondary separation pattern disposed on the second area, disposed between the first and second main separation patterns, and penetrating through the gate electrodes disposed on the second area. The gate electrodes include pad portions on the second area, and the pad portions are thicker than the gate electrodes disposed on the first area and in contact with the at least one secondary separation pattern.
    Type: Grant
    Filed: April 1, 2022
    Date of Patent: February 20, 2024
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Chang Sup Lee, Phil Ouk Nam, Sung Yun Lee, Chang Seok Kang
  • Publication number: 20230420232
    Abstract: Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.
    Type: Application
    Filed: September 7, 2023
    Publication date: December 28, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Tomohiko Kitajima, Ning Li, Chang Seok Kang, Naomi Yoshida
  • Publication number: 20230369031
    Abstract: Methods of manufacturing memory devices are provided. The method comprises pre-cleaning a top surface of a film stack, the film stack comprising alternating layers of a first material layer and a second material layer and having one or more of a memory hole and a slit pattern opening extending through the film stack; exposing the top surface of the film stack to a growth inhibitor; selectively depositing a silicon-containing dielectric layer in a region of the film stack; and densifying the silicon-containing dielectric layer. The processing method is performed in a processing tool without breaking vacuum.
    Type: Application
    Filed: March 28, 2023
    Publication date: November 16, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Tomohiko Kitajima, Ning Li, Chang Seok Kang, Naomi Yoshida
  • Publication number: 20230371246
    Abstract: Described are memory devices having an array region and an extension region adjacent the array region. The array region includes at least two unit cells stacked vertically. The extension region includes a memory stack and a plurality of word line contacts. The memory stack comprises alternating layers of at least one conductive layer, a semiconductor layer, and an insulating layer. The plurality of word line contacts extend through the memory stack to the at least one conductive layer. Each of the plurality of word line contacts have a height that is different than the height of an adjacent word line contact. Each of the plurality of word line contacts has a metallization layer on the top surface. Methods of forming a memory device are described.
    Type: Application
    Filed: May 1, 2023
    Publication date: November 16, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Sung-Kwan Kang, Gill Yong Lee
  • Patent number: 11818877
    Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.
    Type: Grant
    Filed: September 27, 2021
    Date of Patent: November 14, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Sung-Kwan Kang, Fredrick Fishburn, Gill Yong Lee, Nitin K. Ingle
  • Patent number: 11763856
    Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers include a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.
    Type: Grant
    Filed: May 18, 2021
    Date of Patent: September 19, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Sung-Kwan Kang, Gill Yong Lee, Chang Seok Kang
  • Patent number: 11749315
    Abstract: Memory devices are described. The memory devices include a plurality of bit lines extending through a stack of alternating memory layers and dielectric layers. Each of the memory layers comprises a single crystalline-like silicon layer and includes a first word line, a second word line, a first capacitor, and a second capacitor. Methods of forming stacked memory devices are also described.
    Type: Grant
    Filed: December 15, 2021
    Date of Patent: September 5, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sanjay Natarajan, Sung-Kwan Kang, Lequn Liu
  • Publication number: 20230157004
    Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.
    Type: Application
    Filed: January 13, 2023
    Publication date: May 18, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Nitin K. Ingle, Sung-Kwan Kang
  • Publication number: 20230146831
    Abstract: A semiconductor manufacturing process for forming a three-dimensional (3D) memory structure and a semiconductor device having a 3D memory structure is described. The 3D memory structure comprises layers of memory cells with L shaped conductive layers where the L shaped conductive layers of each layer are coupled to metal lines disposed above the top or upper most layer such that the memory cells in each layer can be coupled to control circuitry.
    Type: Application
    Filed: September 4, 2022
    Publication date: May 11, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Gill Yong Lee, Fred Fishburn, Tomohiko Kitajima, Sung-Kwan Kang, Sony Varghese
  • Publication number: 20230096309
    Abstract: Examples herein relate to three-dimensional (3D) dynamic random access memory (DRAM) and corresponding methods. In an example, a film stack is formed on a substrate. The film stack includes multiple unit stacks, each having, sequentially, a first dielectric layer, a semiconductor layer, and a second dielectric layer. A first opening is formed through the film stack. The second dielectric layer is pulled back from the first opening forming a first lateral recess. A gate structure is formed in the first lateral recess and disposed on a portion of the semiconductor layer. A second opening, laterally disposed from where the first opening was formed, is formed through the film stack. The portion of the semiconductor layer is pulled back from the second opening forming a second lateral recess. A capacitor is formed in a region where the second lateral recess was disposed and contacting the portion of the semiconductor layer.
    Type: Application
    Filed: September 27, 2021
    Publication date: March 30, 2023
    Inventors: Chang Seok KANG, Tomohiko KITAJIMA, Sung-Kwan KANG, Fredrick FISHBURN, Gill Yong LEE, Nitin K. INGLE
  • Publication number: 20230101155
    Abstract: A memory device architecture, and method of fabricating a three dimensional device are provided. The memory device architecture may include a plurality of memory blocks, arranged in an array, wherein a given memory block comprises: a cell region, the cell region comprising a three-dimensional array of memory cells, arranged in a plurality of n memory cell layers; and a staircase region, the staircase region being disposed adjacent to at least a first side of the cell region, the staircase region comprising a signal line assembly that is coupled to the three-dimensional array of memory cells.
    Type: Application
    Filed: July 19, 2022
    Publication date: March 30, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Fred Fishburn, Tomohiko Kitajima, Sung-Kwan Kang, Sony Varghese, Gill Yong Lee
  • Patent number: 11594537
    Abstract: Described are memory devices having stacked DRAM cells, resulting in an increase in DRAM cell bit-density. The area of a unit cell is composed of a capacitor, a cell transistor, an isolation region and a connection region, where every capacitor and active region for the cell capacitor is electrically isolated. The memory cells have supporting bars. Methods of forming a memory device are described. The methods include patterning the isolation region with supporting bars, removing non-insulator layers after isolation region patterning, and filling the opened region with an insulator.
    Type: Grant
    Filed: June 22, 2021
    Date of Patent: February 28, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima
  • Patent number: 11587930
    Abstract: Memory devices incorporating bridged word lines are described. The memory devices include a plurality of active regions spaced along a first direction, a second direction and a third direction. A plurality of conductive layers is arranged so that at least one conductive layer is adjacent to at least one side of each of the active regions along the third direction. A conductive bridge extends along the second direction to connect each of the conductive layers to one or more adjacent conductive layer. Some embodiments include an integrated etch stop layer. Methods of forming stacked memory devices are also described.
    Type: Grant
    Filed: January 27, 2021
    Date of Patent: February 21, 2023
    Assignee: APPLIED MATERIALS, INC.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Nitin K. Ingle, Sung-Kwan Kang
  • Patent number: 11587796
    Abstract: Memory devices and methods of manufacturing memory devices are provided. The device and methods described suppress oxidation of metal layers exposed to ambient oxygen. After an opening is formed, a nitridation process occurs to nitridate the surface of the exposed metal layer inside the opening. The nitridated region formed on the surface of metal layer inside the opening works as a barrier layer for oxygen diffusion. In addition, the nitridated region works as an electrode for charge trap memory cells.
    Type: Grant
    Filed: January 13, 2021
    Date of Patent: February 21, 2023
    Assignee: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Sung-Kwan Kang
  • Publication number: 20230044391
    Abstract: Described are memory devices having a metal silicide, resulting in a low resistance contact. Methods of forming a memory device are described. The methods include forming a metal silicide layer on a semiconductor material layer on a memory stack, the semiconductor material layer having a capacitor side and a bit line side. A capacitor is then formed on the capacitor side of the metal silicide layer, and a bit line is formed on the bit line side of the metal silicide layer.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 9, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Nicolas Breil, Chang Seok Kang
  • Publication number: 20230040627
    Abstract: Described is a semiconductor memory device and methods of manufacture. The semiconductor memory device comprises a memory array comprising at least one select-gate-for-drain (SGD) transistor and at least one memory transistor, the memory array having at least one strapping region and at least one strapping contact, the strapping contact connecting a select-gate-for-drain (SGD) transistor to a strapping line.
    Type: Application
    Filed: August 2, 2022
    Publication date: February 9, 2023
    Applicant: Applied Materials, Inc.
    Inventors: Chang Seok Kang, Tomohiko Kitajima, Gill Yong Lee, Sung-Kwan Kang