Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and a silicon germanium region extending into the semiconductor substrate and adjacent to the gate stack. The silicon germanium region has a top surface, with a center portion of the top surface recessed from edge portions of the top surface to form a recess. The edge portions are on opposite sides of the center portion.

Abstract: Provided are a source driver integrated circuit (IC) according to the present disclosure including a first buffer in which first sensing data transmitted from a first source driver IC is stored, a sensing data generation circuit configured to sense a characteristic of a driving element included in each pixel and generate second sensing data, a second buffer in which the second sensing data is stored, a control circuit configured to generate a selection signal in response to an operation command, and a selector configured to transmit one of the first sensing data stored in the first buffer and the second sensing data stored in the second buffer to a second source driver IC in response to the selection signal.

Abstract: A device includes a substrate and a gate structure over the substrate. The device further includes source/drain (S/D) features in the substrate. At least one of the S/D features is located in a trench. The at least one S/D feature includes a first semiconductor material covering an entirety of a bottom surface of the trench. The at least one S/D feature further includes a second semiconductor material over the first semiconductor material. The at least one S/D feature further includes a third semiconductor material over the second semiconductor material. The second semiconductor material has a composition different from the first semiconductor material and the third semiconductor material. The first semiconductor material includes physically discontinuous portions directly contacting the substrate. The second semiconductor material surrounds the third semiconductor material.

Abstract: An integrated circuit structure includes a gate stack over a semiconductor substrate, and an opening extending into the semiconductor substrate, wherein the opening is adjacent to the gate stack. A first silicon germanium region is disposed in the opening, wherein the first silicon germanium region has a first germanium percentage. A second silicon germanium region is over the first silicon germanium region. The second silicon germanium region comprises a portion in the opening. The second silicon germanium region has a second germanium percentage greater than the first germanium percentage. A silicon cap substantially free from germanium is over the second silicon germanium region.

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

Abstract: An apparatus for deploying a display unit includes: a cowl cross bar disposed inside a crash pad; a housing disposed on the cowl cross bar and fastened to a center part of the crash pad; a display unit configured to be deployed along the housing; a rotating unit configured to rotate the housing with respect to the cowl cross bar; a driving unit coupled to the cowl cross bar in order to cause sliding movement of the cowl cross bar; and a controller configured to control at least one of the extent of deployment of the display unit, the amount of sliding movement of the cowl cross bar, or the amount of rotation of the housing.

Abstract: A chart display device for a visual acuity test includes a chart display optical unit that emits a chart image generated by a chart display optical system to a front, and is rotatably coupled to a frame of the chart display device via a rotation shaft; a position indicator light source that indicates the height of an eye to be examined and emits a position identification light; a position detection sensor that detects the position identification light emitted from the position indicator light source, and thus detects the height of the eye to be examined; and a rotation driving unit that rotates the chart display optical unit around the rotation shaft, and thereby tilts an emission direction of the chart image so that the chart image emitted from the chart display optical unit is emitted in the direction of the eye to be examined.

Abstract: A method for forming a semiconductor structure includes forming a gate structure over a substrate. The method also includes forming a spacer on a sidewall of the gate structure. The method also includes forming a source/drain recess beside the spacer. The method also includes treating the source/drain recess and partially removing the spacers in a first cleaning process. The method also includes treating the source/drain recess with a plasma process after performing the first cleaning process. The method also includes treating the source/drain recess in a second cleaning process after treating the source/drain recess with the plasma process. The method also includes forming a source/drain structure in the source/drain recess after performing the second cleaning process.

Abstract: A combined cycle power plant is capable of improving power output and power generation efficiency by cooling intake air supplied to a gas turbine. The plant includes a gas turbine power generation system, an operating fluid power generation system, and a cooling system. The gas turbine power generation system includes an air compressor for compressing air supplied through an air incoming path, a gas turbine for generating rotary power by burning a mixture of fuel and the air compressed by the air compressor, and a first generator for generating electricity by using the rotary power of the gas turbine. The operating fluid power generation system heats an operating fluid by using combustion gas discharged from the gas turbine and generates electricity using the heated operating fluid. The cooling system cools air supplied from the air compressor by supplying the operating fluid to an upstream side of the air compressor.

Abstract: A method includes forming a fin over a substrate, forming an isolation region adjacent the fin, forming a dummy gate structure over the fin, and recessing the fin adjacent the dummy gate structure to form a first recess using a first etching process. The method also includes performing a plasma clean process on the first recess, the plasma clean process including placing the substrate on a holder disposed in a process chamber, heating the holder to a process temperature between 300° C. and 1000° C., introducing hydrogen gas into a plasma generation chamber connected to the process chamber, igniting a plasma within the plasma generation chamber to form hydrogen radicals, and exposing surfaces of the recess to the hydrogen radicals. The method also includes epitaxially growing a source/drain region in the first recess.

Abstract: A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer.

Abstract: A roof air bag apparatus for a vehicle includes a roof air bag cushion protecting a passenger, and the roof air bag cushion can be separated into a front air bag cushion and a rear air bag cushion. In particular, the front air bag cushion and the rear air bag cushion are unfolded into a space between a front passenger and a rear passenger in a face-to-face mode at the time of occurrence of a car accident, such that the unfolded front air bag cushion protects the front passenger by absorbing an impact force, and the unfolded rear air bag cushion protects the rear passenger by absorbing an impact force.

Abstract: A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.

Abstract: Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.

Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for acquiring X coordinates and Y coordinate emission data for acquiring Y coordinates of the touch coordinates, a selection circuit configured to time-divide 1 frame duration, to output image data to a display driving circuit during a display field, to output the X coordinate emission data to the display driving circuit during an X coordinate field, and to output the Y coordinate emission data to the display driving circuit during a Y coordinate field, and a control data generation circuit configured to generate source control data and gate control data for outputting the image data, the X coordinate emission data, and the Y coordinate emission data to a display panel and to output the source control data and the gate control data to the display driving circuit.

Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for acquiring X coordinates and Y coordinate emission data for acquiring Y coordinates of touch coordinates, a selection circuit configured to time-divide 1 frame duration, to output the X coordinate emission data to a display driving circuit during an X coordinate field, and to output the Y coordinate emission data to the display driving circuit during a Y coordinate field, and a control data generation circuit configured to output control data for allowing each pixel to emit light in units of data line groups including i data lines using the X coordinate emission data during the X coordinate field and for allowing each pixel to emit light in units of gate lines including j gate lines using the Y coordinate emission data during the Y coordinate field, to the display driving circuit.

Abstract: A method includes forming a semiconductor fin protruding higher than top surfaces of isolation regions. A top portion of the semiconductor fin is formed of a first semiconductor material. A semiconductor cap layer is formed on a top surface and sidewalls of the semiconductor fin. The semiconductor cap layer is formed of a second semiconductor material different from the first semiconductor material. The method further includes forming a gate stack on the semiconductor cap layer, forming a gate spacer on a sidewall of the gate stack, etching a portion of the semiconductor fin on a side of the gate stack to form a first recess extending into the semiconductor fin, recessing the semiconductor cap layer to form a second recess directly underlying a portion of the gate spacer, and performing an epitaxy to grow an epitaxy region extending into both the first recess and the second recess.

Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for acquiring X coordinates and Y coordinate emission data for acquiring Y coordinates, a selection circuit configured to time-divide 1 frame duration to output the X coordinate emission data to a display driving circuit during an X coordinate field and to output the Y coordinate emission data to the display driving circuit during a Y coordinate field, and a control data generation circuit configured to output control data for allowing pixels connected to one data line to emit light in units of 1 data line using the X coordinate emission data during the X coordinate field and allowing pixels connected to one gate line to emit light in units of 1 gate line using the Y coordinate emission data during the Y coordinate field, to the display driving circuit.

Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes forming a source/drain recess adjacent to the gate structure. The method also includes wet cleaning the source/drain recess in a first wet cleaning process. The method also includes treating the source/drain recess with a plasma process. The method also includes wet cleaning the source/drain recess in a second wet cleaning process after treating the source/drain recess via the plasma process. The method also includes growing a source/drain epitaxial structure in the source/drain recess.

Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.