Patents by Inventor Chang Sung
Chang Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11897416Abstract: A seat belt to increase a force for restraining a passenger's lower body in a sitting state of a relaxation mode while satisfying existing laws in a normal sitting state and to a movement control method thereof includes an anchor unit provided on a lower portion of a first side surface of a seat and configured for allowing webbing of the seat belt to be locked thereto and an anchor moving apparatus configured to move the anchor unit forwards and backwards thereof, and to a movement control method thereof.Type: GrantFiled: June 16, 2022Date of Patent: February 13, 2024Assignees: Hyundai Motor Company, Kia Corporation, SAMSONG INDUSTRIES, LTD.Inventors: Dae Woon Kim, Il Chang Sung, Won Ryong Song, Jung Woo Park
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Epitaxial fin structures of finFET having an epitaxial buffer region and an epitaxial capping region
Patent number: 11888046Abstract: A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.Type: GrantFiled: November 1, 2021Date of Patent: January 30, 2024Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.Inventors: Hsueh-Chang Sung, Kun-Mu Li -
Patent number: 11851019Abstract: Embodiments of the present disclosure relate to a vehicle seat airbag apparatus, wherein: when a side collision accident occurs, an active vent hole is closed to delay the deployment speed of a front cushion and thus to enable a side cushion so as to have sufficient internal pressure, thereby improving ability to respond to a side collision; and when a frontal collision accident occurs, the active vent hole maintains an open state to rapidly deploy the front cushion, thereby improving ability to respond to a frontal collision.Type: GrantFiled: July 28, 2022Date of Patent: December 26, 2023Assignees: Hyundai Motor Company, Kia Corporation, Hyundai Mobis Co., Ltd.Inventors: Il Chang Sung, Sang Won Hwangbo
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Patent number: 11851018Abstract: A seat airbag apparatus for a vehicle and a method of controlling the operation thereof, includes side cushions deployed from the seatback, front cushions configured to be deployed from the side cushions, and inflators for the side cushions and inflators for the front cushions. The deployment operation of the side cushions and the deployment operation of the front cushions are respectively controlled depending on a normal seating mode and a relax mode of an occupant and a side collision and a front collision of the vehicle.Type: GrantFiled: June 14, 2022Date of Patent: December 26, 2023Assignees: HYUNDAI MOTOR COMPANY, KIA CORPORATION, HYUNDAI MOBIS CO., LTD.Inventors: Il Chang Sung, Sang Won Hwangbo
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Publication number: 20230402326Abstract: In an embodiment, a method includes forming a first fin and a second fin within an insulation material over a substrate, the first fin and the second fin includes different materials, the insulation material being interposed between the first fin and the second fin, the first fin having a first width and the second fin having a second width; forming a first capping layer over the first fin; and forming a second capping layer over the second fin, the first capping layer having a first thickness, the second capping layer having a second thickness different from the first tType: ApplicationFiled: August 8, 2023Publication date: December 14, 2023Inventors: Hung-Yao Chen, Pin-Chu Liang, Hsueh-Chang Sung, Pei-Ren Jeng, Yee-Chia Yeo
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Publication number: 20230369129Abstract: A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer.Type: ApplicationFiled: July 25, 2023Publication date: November 16, 2023Inventors: Wei-Min Liu, Hsueh-Chang Sung, Yee-Chia Yeo
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Publication number: 20230369491Abstract: The present disclosure relates to an integrated chip. The integrated chip includes a gate structure arranged over a substrate and a source/drain region arranged within the substrate along a side of the gate structure. The source/drain region includes a first layer lining interior sidewalls and a horizontally extending surface of the substrate, and a second layer lining interior sidewalls and a horizontally extending surface of the first layer. The first layer has a dopant with a first dopant concentration that continually decreases from an outermost sidewall of the first layer facing the substrate to one of the interior sidewalls of the first layer.Type: ApplicationFiled: July 26, 2023Publication date: November 16, 2023Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
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Publication number: 20230352589Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium conType: ApplicationFiled: July 3, 2023Publication date: November 2, 2023Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung
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Patent number: 11804408Abstract: A method includes forming a gate structure over fins protruding from a semiconductor substrate; forming an isolation region surrounding the fins; depositing a spacer layer over the gate structure and over the fins, wherein the spacer layer fills the regions extending between pairs of adjacent fins; performing a first etch on the spacer layer, wherein after performing the first etch, first remaining portions of the spacer layer that are within inner regions extending between pairs of adjacent fins have a first thickness and second remaining portions of the spacer layer that are not within the inner regions have a second thickness less than the first thickness; and forming an epitaxial source/drain region adjacent the gate structure and extending over the fins, wherein portions of the epitaxial source/drain region within the inner regions are separated from the first remaining portions of the spacer layer.Type: GrantFiled: May 27, 2022Date of Patent: October 31, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Wei-Min Liu, Hsueh-Chang Sung, Yee-Chia Yeo
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Patent number: 11791791Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.Type: GrantFiled: June 21, 2021Date of Patent: October 17, 2023Inventors: Seunghwan Hong, Yoo-Chang Sung, Wangsoo Kim, Indal Song
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Publication number: 20230294630Abstract: Provided is a roof-mounted airbag configured to reduce the risk of injury to a passenger by minimizing movement of a cushion when the passenger is placed on the cushion. The roof-mounted airbag includes a cushion, formed in a cylindrical shape and configured to be deployed downwards between passengers facing each other while left and right upper ends thereof are fixed to a roof part, and an inflator configured to provide gas to an inside of the cushion.Type: ApplicationFiled: August 29, 2022Publication date: September 21, 2023Inventors: Il Chang Sung, Byung Ho Min
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Patent number: 11749752Abstract: The present disclosure relates to a method of forming a transistor device. The method may be performed by forming a gate structure onto a semiconductor substrate and forming a source/drain recess within the semiconductor substrate adjacent to a side of the gate structure. One or more strain inducing materials are formed within the source/drain recess. The one or more strain inducing materials include a strain inducing component with a strain inducing component concentration profile that continuously decreases from a bottommost surface of the one or more strain inducing materials to a position above the bottommost surface. The bottommost surface contacts the semiconductor substrate.Type: GrantFiled: December 3, 2020Date of Patent: September 5, 2023Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.Inventors: Hsueh-Chang Sung, Tsz-Mei Kwok, Kun-Mu Li, Tze-Liang Lee, Chii-Horng Li
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Publication number: 20230275153Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.Type: ApplicationFiled: May 2, 2023Publication date: August 31, 2023Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee, Jyun-Chih Lin, Tzu-Hsiang Hsu, Feng-Cheng Yang
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Patent number: 11735668Abstract: An embodiment is a semiconductor structure. The semiconductor structure includes a substrate. A fin is on the substrate. The fin includes silicon germanium. An interfacial layer is over the fin. The interfacial layer has a thickness in a range from greater than 0 nm to about 4 nm. A source/drain region is over the interfacial layer. The source/drain region includes silicon germanium.Type: GrantFiled: July 28, 2022Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chih-Yun Chin, Chii-Horng Li, Chien-Wei Lee, Hsueh-Chang Sung, Heng-Wen Ting, Roger Tai, Pei-Ren Jeng, Tzu-Hsiang Hsu, Yen-Ru Lee, Yan-Ting Lin, Davie Liu
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Patent number: 11735664Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium conType: GrantFiled: August 30, 2021Date of Patent: August 22, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung
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Patent number: 11710777Abstract: A method of forming a semiconductor device includes depositing a film over a dielectric layer. The dielectric layer is over a first fin, a second fin, and within a trench between the first fin and the second fin. The method further includes etching top portions of the film, performing a treatment on the dielectric layer to remove impurities after etching the top portions of the film, and filling the trench over the remaining portions of the film. The treatment includes bombarding the dielectric layer with radicals.Type: GrantFiled: October 27, 2020Date of Patent: July 25, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.Inventors: Chia-Ao Chang, De-Wei Yu, Chii-Horng Li, Yee-Chia Yeo, Hsueh-Chang Sung, Pei-Ren Jeng
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Publication number: 20230231052Abstract: A semiconductor device and a method of forming the same are provided. The semiconductor device includes a gate stack over an active region and a source/drain region in the active region adjacent the gate stack. The source/drain region includes a first semiconductor layer having a first germanium concentration and a second semiconductor layer over the first semiconductor layer. The second semiconductor layer has a second germanium concentration greater than the first germanium concentration. The source/drain region further includes a third semiconductor layer over the second semiconductor layer and a fourth semiconductor layer over the third semiconductor layer. The third semiconductor layer has a third germanium concentration greater than the second germanium concentration. The fourth semiconductor layer has a fourth germanium concentration less than the third germanium concentration.Type: ApplicationFiled: March 20, 2023Publication date: July 20, 2023Inventors: Kun-Mu Li, Hsueh-Chang Sung
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Publication number: 20230223941Abstract: Disclosed is a frequency divider which includes a frequency dividing core circuit that includes a plurality of transistors and is configured to generate at least one division clock signal based on a clock signal and an inverted clock signal, a controller that is configured to generate a body bias control signal based on clock frequency information, and an adaptive body bias (ABB) generator that is configured to generate at least one body bias based on the body bias control signal and configured to apply the at least one body bias to a body of one or more of the plurality of transistors.Type: ApplicationFiled: September 14, 2022Publication date: July 13, 2023Inventors: Jaewoo Lee, Yoo-Chang Sung, Jeongdon Ihm, Hojun Chang, Jinseok Heo
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Publication number: 20230207396Abstract: A semiconductor device includes a first device region and a second device region. The first device region includes a first source/drain region extending from a substrate and a first and a second pair of spacers. The first source/drain region extends between the first pair of spacers and the second pair of spacers. The first pair of spacers and the second pair of spacers have a first height. The second device region includes a second and a third source/drain region extending from the substrate and a third and a fourth pair of spacers. The third source/drain region is separate from the second source/drain region. The second source/drain region extends between the third pair of spacers. The third source/drain region extends between the fourth pair of spacers. The third pair of spacers and the fourth pair of spacers have a second height greater than the first height.Type: ApplicationFiled: March 6, 2023Publication date: June 29, 2023Inventors: Wei-Min Liu, Hsueh-Chang Sung, Li-Li Su, Yee-Chia Yeo
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Patent number: 11677027Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.Type: GrantFiled: July 9, 2021Date of Patent: June 13, 2023Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee, Jyun-Chih Lin, Tzu-Hsiang Hsu, Feng-Cheng Yang