Patents by Inventor Chang Sung

Chang Sung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20220059676
    Abstract: A fin structure on a substrate is disclosed. The fin structure can comprises a first epitaxial region and a second epitaxial region separated by a dielectric region, a merged epitaxial region on the first epitaxial region and the second epitaxial region, an epitaxial buffer region on a top surface of the merged epitaxial region, and an epitaxial capping region on the buffer epitaxial region and side surfaces of the merged epitaxial region.
    Type: Application
    Filed: November 1, 2021
    Publication date: February 24, 2022
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang SUNG, Kun-Mu Li
  • Patent number: 11249662
    Abstract: A memory module includes a plurality of semiconductor memory devices associated with a same module board. The plurality of semiconductor memory devices configured to simultaneously perform a training operation, the plurality of semiconductor memory devices including a reception interface circuit configured to perform the training operation to search for selected equalization coefficients of an equalizer based on a training pattern from a memory controller, and transmit a training information signal to the memory controller in a training mode in response to a training command from the memory controller, the training information signal including the selected equalization coefficients.
    Type: Grant
    Filed: June 29, 2020
    Date of Patent: February 15, 2022
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Wang-Soo Kim, Jung-Hwan Choi, Ki-Duk Park, Yoo-Chang Sung, Jin-Sung Youn, Chang-Kyo Lee, Ju-Ho Jeon, Jin-Seok Heo
  • Patent number: 11232499
    Abstract: An apparatus that provides a cooperative shopping service in association with a chat application includes a friend information receiving unit configured to receive, from a host device, information about at least one friend or chat room selected from a list of multiple friends or multiple chat rooms managed by the chat application; an invitation unit configured to transmit an invitation message to a guest device corresponding to the friend or a member of the chat room through the chat application; and a cooperative shopping service providing unit configured to provide, both to the host device and the guest device, a list of products that are capable of being put into a shopping cart of the host device and receive order information about product selected from the list of products by at least one of the host device and the guest device, wherein the list of products provided to the host device and the guest device is generated based on a location of a delivery destination determined by the host device.
    Type: Grant
    Filed: April 16, 2018
    Date of Patent: January 25, 2022
    Assignee: KAKAO CORP.
    Inventors: Do Yon Hwang, Kyoung Jin Han, Jun Hwan Lee, Dong Wha Yuk, Woo Yeol Baek, Ji Yoong Choi, Ji Yeon Shin, Yeon Hee Shin, Mi Ran Kang, Sheung Min Shin, Yun Ji Koh, Du Hyeong Kim, Chang Sung Ban, Hyun Hee Park, Ji Eun Kim, Jin Young Choi
  • Patent number: 11222584
    Abstract: Disclosed is a timing controller including a coordinate data generation circuit configured to generate X coordinate emission data for each data line group and Y coordinate emission data for each gate line group, a selection circuit configured to output the X coordinate emission data during an X coordinate field and to output the Y coordinate emission data during a Y coordinate field, and a control data generation circuit configured to output control data for allowing each pixel to emit light in units of the data line groups based on the X coordinate emission data during the X coordinate field and allowing each pixel to emit light in units of the gate line groups based on the Y coordinate emission data during the Y coordinate field, wherein the X coordinate emission data for each data line group and the Y coordinate emission data for each gate line group have random color.
    Type: Grant
    Filed: February 8, 2021
    Date of Patent: January 11, 2022
    Assignee: SILICON WORKS CO., LTD.
    Inventors: You Jin Kwon, Sang Kwon Kim, Chang Sung Hong, Pyeong Keun Oh, Jun Ho Kwak
  • Patent number: 11217672
    Abstract: Embodiments provide a way of treating source/drain recesses with a high heat treatment and an optional hydrogen plasma treatment. The high heat treatment smooths the surfaces inside the recesses and remove oxides and etching byproducts. The hydrogen plasma treatment enlarges the recesses vertically and horizontally and inhibits further oxidation of the surfaces in the recesses.
    Type: Grant
    Filed: November 8, 2019
    Date of Patent: January 4, 2022
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee
  • Publication number: 20210402949
    Abstract: A seat airbag apparatus for a vehicle is disclosed. A side cushion is deployed so as to protrude forward from a seatback in order to protect the lateral sides of an occupant, and a front cushion is deployed so as to protrude from the side cushion to the front of the occupant in order to protect the front side of the occupant. The deployment of the side cushion and the front cushion is limited by an upper dual-surface tether structure, formed by an upper-side surface tether and an upper-front surface tether, and a lower dual-surface tether structure, formed by a lower-side surface tether and a lower-front surface tether, thereby increasing force with which movement of the occupant is restricted, thus further enhancing an occupant protection effect.
    Type: Application
    Filed: November 12, 2020
    Publication date: December 30, 2021
    Applicants: HYUNDAI MOTOR COMPANY, KIA MOTORS CORPORATION, HYUNDAI MOBIS CO., LTD.
    Inventors: Il Chang SUNG, Sang Won HWANGBO, Choong Ryung LEE
  • Patent number: 11211473
    Abstract: A method of forming a semiconductor device having first and second fin structures on a substrate includes forming a first epitaxial region of the first fin structure and forming a second epitaxial region of the second fin structure. The method further includes forming a buffer region on the first epitaxial region of the first fin structure and performing an etch process to etch back a portion of the second epitaxial region. The buffer region helps to prevents etch back of a top surface of the first epitaxial region during the etch process. Further, a capping region is formed on the buffer region and the etched second epitaxial region.
    Type: Grant
    Filed: June 22, 2020
    Date of Patent: December 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Sung, Kun-Mu Li
  • Publication number: 20210391456
    Abstract: A method includes forming a semiconductor fin over a substrate, etching the semiconductor fin to form a recess, wherein the recess extends into the substrate, and forming a source/drain region in the recess, wherein forming the source/drain region includes epitaxially growing a first semiconductor material on sidewalls of the recess, wherein the first semiconductor material includes silicon germanium, wherein the first semiconductor material has a first germanium concentration from 10 to 40 atomic percent, epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium, wherein the second semiconductor material has a second germanium concentration that is greater than the first germanium concentration, and epitaxially growing a third semiconductor material over the second semiconductor material, the third semiconductor material including silicon germanium, wherein the third semiconductor material has a third germanium con
    Type: Application
    Filed: August 30, 2021
    Publication date: December 16, 2021
    Inventors: Kun-Mu Li, Heng-Wen Ting, Yen-Ru Lee, Hsueh-Chang Sung
  • Publication number: 20210371257
    Abstract: An up-and-down driving device allows an up-and-down driving unit to move while supporting an object's load, in a support module in which the up-and-down driving unit is movably inserted into an inner space of a fixed housing. The up-and-down driving device includes: a driving means for moving the up-and-down driving unit in an up-and-down direction; a fixed-position compression spring main module including a fixed-position compression spring having one side fixed to a lower end of the housing and the other side supporting the up-and-down driving unit and mounted in a motion direction of the up-and-down driving unit; and a variable-position compression spring supplemental module including a variable-position compression spring having one side mounted rotatably to a side of the housing and the other side fastened rotatably to the up-and-down driving unit and configured to rotate while making a predetermined angle with the motion direction of the up-and-down driving unit.
    Type: Application
    Filed: May 24, 2021
    Publication date: December 2, 2021
    Inventors: Chang Sung KIM, Young Woo LEE
  • Publication number: 20210351081
    Abstract: A device includes a fin over a substrate, the fin including a first end and a second end, wherein the first end of the fin has a convex profile, an isolation region adjacent the fin, a gate structure along sidewalls of the fin and over the top surface of the fin, a gate spacer laterally adjacent the gate structure, and an epitaxial region adjacent the first end of the fin.
    Type: Application
    Filed: July 22, 2021
    Publication date: November 11, 2021
    Inventors: Kun-Mu Li, Heng-Wen Ting, Hsueh-Chang Sung, Yen-Ru Lee, Chien-Wei Lee
  • Patent number: 11171209
    Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching one or more semiconductor fins to form one or more recesses; and forming a source/drain region in the one ore more recesses, the forming the source/drain region including epitaxially growing a first semiconductor material in the one or more recesses at a temperature of 600° C. to 800° C., the first semiconductor material including doped silicon germanium; and conformally depositing a second semiconductor material over the first semiconductor material at a temperature of 300° C. to 600° C., the second semiconductor material including doped silicon germanium and having a different composition than the first semiconductor material.
    Type: Grant
    Filed: August 22, 2019
    Date of Patent: November 9, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Heng-Wen Ting, Kei-Wei Chen, Chii-Horng Li, Pei-Ren Jeng, Hsueh-Chang Sung, Yen-Ru Lee, Chun-An Lin
  • Patent number: 11164944
    Abstract: A semiconductor device having an improved source/drain region profile and a method for forming the same are disclosed. In an embodiment, a method includes etching a semiconductor fin to form a first recess; and forming a source/drain region in the first recess, forming the source/drain region including epitaxially growing a first semiconductor material in the first recess, the first semiconductor material being silicon; epitaxially growing a second semiconductor material over the first semiconductor material, the second semiconductor material including silicon germanium; and epitaxially growing a third semiconductor material over the second semiconductor material, and the third semiconductor material having a germanium concentration from 60 to 80 atomic percent, the third semiconductor material having a germanium concentration greater than the germanium concentration of the second semiconductor material.
    Type: Grant
    Filed: August 16, 2019
    Date of Patent: November 2, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Heng-Wen Ting, Hsueh-Chang Sung
  • Publication number: 20210336048
    Abstract: A semiconductor device including a source/drain region having a V-shaped bottom surface and extending below gate spacers adjacent a gate stack and a method of forming the same are disclosed. In an embodiment, a method includes forming a gate stack over a fin; forming a gate spacer on a sidewall of the gate stack; etching the fin with a first anisotropic etch process to form a first recess adjacent the gate spacer; etching the fin with a second etch process using etchants different from the first etch process to remove an etching residue from the first recess; etching surfaces of the first recess with a third anisotropic etch process using etchants different from the first etch process to form a second recess extending below the gate spacer and having a V-shaped bottom surface; and epitaxially forming a source/drain region in the second recess.
    Type: Application
    Filed: July 9, 2021
    Publication date: October 28, 2021
    Inventors: Chien-Wei Lee, Hsueh-Chang Sung, Yen-Ru Lee, Jyun-Chih Lin, Tzu-Hsiang Hsu, Feng-Cheng Yang
  • Patent number: 11158508
    Abstract: A fin field device structure and method for forming the same are provided. The FinFET device structure includes a protruding structure extending from a substrate and an anti-punch through implant (APT) region formed in the protruding structure. The FinFET device structure includes a barrier layer formed on the APT region, and the barrier layer has a width in a horizontal direction. The width gradually tapers from a bottom of the barrier layer to a top of the barrier layer.
    Type: Grant
    Filed: March 12, 2018
    Date of Patent: October 26, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Tsung-Yao Wen, Sheng-Chen Wang, Sai-Hooi Yeong, Hsueh-Chang Sung, Ya-Yun Cheng
  • Publication number: 20210327708
    Abstract: Proposed is a precursor composition for forming a metal film including a zirconium compound represented by any one of Chemical Formulas 1 to 3 and a hafnium compound represented by any one of Chemical Formulas 4 to 6.
    Type: Application
    Filed: December 6, 2019
    Publication date: October 21, 2021
    Inventors: Chang Sung HONG, Yong Joo PARK, Tae Hoon OH, In Chun HWANG, Sang Kyung LEE, Dong Hyun KIM
  • Patent number: 11145759
    Abstract: A source/drain (S/D) structure includes a SiGe structure epitaxially grown and having sloped facets on a recessed fin structure disposed adjacent to a channel portion of a finFET, a first Ge structure having a rounded surface epitaxially grown on the SiGe structure, and a capping layer formed over the rounded surface of the Ge structure. The capping layer may be formed of Si. Such S/D structures provide both a larger physical size for lower contact resistance, and greater volume and concentration of Ge for higher compressive strain applied to the channel portion of the finFET.
    Type: Grant
    Filed: October 12, 2017
    Date of Patent: October 12, 2021
    Assignee: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Hsueh-Chang Sung, Liang-Yi Chen
  • Publication number: 20210313945
    Abstract: A receiver includes an amplifier that receives a transmission signal and amplifies a first voltage difference between the transmission signal and a reference signal to generate a first output signal and a second output signal at a first node and a second node. An equalizer is provided, which is connected to the first node and the second node and receives the transmission signal. The equalizer compensates a common-mode offset between the first output signal and the second output signal based on a second voltage difference between an average voltage level of the transmission signal and the reference signal.
    Type: Application
    Filed: June 21, 2021
    Publication date: October 7, 2021
    Inventors: Seunghwan Hong, Yoo-Chang Sung, Wangsoo Kim, Indal Song
  • Publication number: 20210313443
    Abstract: A method for forming a fin field effect transistor device structure includes forming a fin structure over a substrate. The method also includes forming a gate structure across the fin structure. The method also includes forming a source/drain recess adjacent to the gate structure. The method also includes wet cleaning the source/drain recess in a first wet cleaning process. The method also includes treating the source/drain recess with a plasma process. The method also includes wet cleaning the source/drain recess in a second wet cleaning process after treating the source/drain recess via the plasma process. The method also includes growing a source/drain epitaxial structure in the source/drain recess.
    Type: Application
    Filed: April 1, 2020
    Publication date: October 7, 2021
    Applicant: Taiwan Semiconductor Manufacturing Co., Ltd.
    Inventors: Chien-Wei LEE, Yen-Ru LEE, Hsueh-Chang SUNG, Yee-Chia YEO
  • Publication number: 20210301401
    Abstract: A precursor solution for thin-film deposition including a functional solvent selected from among liquid alkene and liquid alkyne capable of dissolving a metal halide at room temperature and a metal halide dissolved in the functional solvent and existing as a liquid at room temperature, thereby solving problems caused by halogen gas generated in a chamber during a deposition process and improving the uniformity of the thickness of a thin film.
    Type: Application
    Filed: May 25, 2021
    Publication date: September 30, 2021
    Inventors: Yong Joo PARK, Han Sol OH, In Chun HWANG, Sang Ho KIM, Chang Sung HONG, Sang Kyung LEE
  • Patent number: 11133416
    Abstract: In an embodiment, a device includes: a fin extending from a substrate; a gate stack over a channel region of the fin; and a source/drain region in the fin adjacent the channel region, the source/drain region including: a first epitaxial layer contacting sidewalls of the fin, the first epitaxial layer including silicon and germanium doped with a dopant, the first epitaxial layer having a first concentration of the dopant; and a second epitaxial layer on the first epitaxial layer, the second epitaxial layer including silicon and germanium doped with the dopant, the second epitaxial layer having a second concentration of the dopant, the second concentration being greater than the first concentration, the first epitaxial layer and the second epitaxial layer having a same germanium concentration.
    Type: Grant
    Filed: August 23, 2019
    Date of Patent: September 28, 2021
    Assignee: Taiwan Semiconductor Manufacturing Company, Ltd.
    Inventors: Yan-Ting Lin, Hsueh-Chang Sung, Yen-Ru Lee